AuxXxilium/linux_dsm_epyc7002
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linux_dsm_epyc7002/arch/x86/kernel/acpi
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Tony W Wang-oc f8c0e061cb x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3 
Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.

Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: "hpa@zytor.com" <hpa@zytor.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
Cc: "rjw@rjwysocki.net" <rjw@rjwysocki.net>
Cc: "lenb@kernel.org" <lenb@kernel.org>
Cc: David Wang <DavidWang@zhaoxin.com>
Cc: "Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>
Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>
Cc: "Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Link: https://lkml.kernel.org/r/a370503660994669991a7f7cda7c5e98@zhaoxin.com
2019-06-22 11:45:58 +02:00
..
apei.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
boot.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 156 2019-05-30 11:26:35 -07:00
cppc_msr.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
cstate.c x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3 2019-06-22 11:45:58 +02:00
Makefile
sleep.c
sleep.h
wakeup_32.S treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 430 2019-06-05 17:37:16 +02:00
wakeup_64.S treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 430 2019-06-05 17:37:16 +02:00