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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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fd968973de
Add phy driver for the Rockchip DisplayPort PHY module. This is required to get DisplayPort working in Rockchip SoCs. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
152 lines
3.7 KiB
C
152 lines
3.7 KiB
C
/*
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* Rockchip DP PHY driver
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*
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* Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
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* Author: Yakir Yang <ykk@@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define GRF_SOC_CON12 0x0274
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#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
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#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
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#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
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#define GRF_EDP_PHY_SIDDQ_ON 0
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#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
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struct rockchip_dp_phy {
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struct device *dev;
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struct regmap *grf;
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struct clk *phy_24m;
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};
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static int rockchip_set_phy_state(struct phy *phy, bool enable)
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{
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struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
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int ret;
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if (enable) {
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ret = regmap_write(dp->grf, GRF_SOC_CON12,
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GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
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GRF_EDP_PHY_SIDDQ_ON);
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if (ret < 0) {
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dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(dp->phy_24m);
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} else {
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clk_disable_unprepare(dp->phy_24m);
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ret = regmap_write(dp->grf, GRF_SOC_CON12,
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GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
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GRF_EDP_PHY_SIDDQ_OFF);
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}
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return ret;
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}
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static int rockchip_dp_phy_power_on(struct phy *phy)
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{
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return rockchip_set_phy_state(phy, true);
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}
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static int rockchip_dp_phy_power_off(struct phy *phy)
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{
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return rockchip_set_phy_state(phy, false);
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}
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static const struct phy_ops rockchip_dp_phy_ops = {
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.power_on = rockchip_dp_phy_power_on,
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.power_off = rockchip_dp_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int rockchip_dp_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct phy_provider *phy_provider;
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struct rockchip_dp_phy *dp;
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struct phy *phy;
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int ret;
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if (!np)
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return -ENODEV;
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dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
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if (IS_ERR(dp))
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return -ENOMEM;
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dp->dev = dev;
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dp->phy_24m = devm_clk_get(dev, "24m");
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if (IS_ERR(dp->phy_24m)) {
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dev_err(dev, "cannot get clock 24m\n");
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return PTR_ERR(dp->phy_24m);
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}
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ret = clk_set_rate(dp->phy_24m, 24000000);
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if (ret < 0) {
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dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
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return ret;
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}
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dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
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if (IS_ERR(dp->grf)) {
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dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
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return PTR_ERR(dp->grf);
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}
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ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
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GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
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if (ret != 0) {
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dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
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return ret;
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}
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phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
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if (IS_ERR(phy)) {
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dev_err(dev, "failed to create phy\n");
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return PTR_ERR(phy);
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}
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phy_set_drvdata(phy, dp);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
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{ .compatible = "rockchip,rk3288-dp-phy" },
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{}
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};
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MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
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static struct platform_driver rockchip_dp_phy_driver = {
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.probe = rockchip_dp_phy_probe,
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.driver = {
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.name = "rockchip-dp-phy",
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.of_match_table = rockchip_dp_phy_dt_ids,
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},
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};
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module_platform_driver(rockchip_dp_phy_driver);
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MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip DP PHY driver");
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MODULE_LICENSE("GPL v2");
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