mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 22:24:56 +07:00
e1eb899b45
Add the IOCTL interface so that applications can allocate per VM BOs. Still WIP since not all corner cases are tested yet, but this reduces average CS overhead for 10K BOs from 21ms down to 48us. v2: add some extra checks, remove the WIP tag v3: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
421 lines
10 KiB
C
421 lines
10 KiB
C
/*
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* Copyright © 2007 David Airlie
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* David Airlie
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "cikd.h"
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#include <drm/drm_fb_helper.h>
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#include <linux/vga_switcheroo.h>
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/* object hierarchy -
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this contains a helper + a amdgpu fb
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the helper contains a pointer to amdgpu framebuffer baseclass.
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*/
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struct amdgpu_fbdev {
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struct drm_fb_helper helper;
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struct amdgpu_framebuffer rfb;
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struct amdgpu_device *adev;
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};
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static int
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amdgpufb_open(struct fb_info *info, int user)
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{
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struct amdgpu_fbdev *rfbdev = info->par;
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struct amdgpu_device *adev = rfbdev->adev;
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int ret = pm_runtime_get_sync(adev->ddev->dev);
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if (ret < 0 && ret != -EACCES) {
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pm_runtime_mark_last_busy(adev->ddev->dev);
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pm_runtime_put_autosuspend(adev->ddev->dev);
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return ret;
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}
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return 0;
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}
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static int
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amdgpufb_release(struct fb_info *info, int user)
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{
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struct amdgpu_fbdev *rfbdev = info->par;
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struct amdgpu_device *adev = rfbdev->adev;
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pm_runtime_mark_last_busy(adev->ddev->dev);
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pm_runtime_put_autosuspend(adev->ddev->dev);
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return 0;
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}
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static struct fb_ops amdgpufb_ops = {
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.owner = THIS_MODULE,
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DRM_FB_HELPER_DEFAULT_OPS,
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.fb_open = amdgpufb_open,
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.fb_release = amdgpufb_release,
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.fb_fillrect = drm_fb_helper_cfb_fillrect,
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.fb_copyarea = drm_fb_helper_cfb_copyarea,
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.fb_imageblit = drm_fb_helper_cfb_imageblit,
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};
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int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
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{
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int aligned = width;
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int pitch_mask = 0;
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switch (cpp) {
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case 1:
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pitch_mask = 255;
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break;
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case 2:
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pitch_mask = 127;
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break;
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case 3:
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case 4:
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pitch_mask = 63;
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break;
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}
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aligned += pitch_mask;
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aligned &= ~pitch_mask;
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return aligned * cpp;
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}
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static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
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{
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struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
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int ret;
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ret = amdgpu_bo_reserve(abo, true);
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if (likely(ret == 0)) {
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amdgpu_bo_kunmap(abo);
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amdgpu_bo_unpin(abo);
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amdgpu_bo_unreserve(abo);
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}
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drm_gem_object_put_unlocked(gobj);
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}
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static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
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struct drm_mode_fb_cmd2 *mode_cmd,
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struct drm_gem_object **gobj_p)
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{
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struct amdgpu_device *adev = rfbdev->adev;
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struct drm_gem_object *gobj = NULL;
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struct amdgpu_bo *abo = NULL;
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bool fb_tiled = false; /* useful for testing */
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u32 tiling_flags = 0;
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int ret;
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int aligned_size, size;
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int height = mode_cmd->height;
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u32 cpp;
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cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
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/* need to align pitch with crtc limits */
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mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
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fb_tiled);
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height = ALIGN(mode_cmd->height, 8);
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size = mode_cmd->pitches[0] * height;
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aligned_size = ALIGN(size, PAGE_SIZE);
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ret = amdgpu_gem_object_create(adev, aligned_size, 0,
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AMDGPU_GEM_DOMAIN_VRAM,
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AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
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AMDGPU_GEM_CREATE_VRAM_CLEARED,
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true, NULL, &gobj);
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if (ret) {
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pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
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return -ENOMEM;
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}
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abo = gem_to_amdgpu_bo(gobj);
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if (fb_tiled)
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tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
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ret = amdgpu_bo_reserve(abo, false);
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if (unlikely(ret != 0))
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goto out_unref;
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if (tiling_flags) {
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ret = amdgpu_bo_set_tiling_flags(abo,
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tiling_flags);
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if (ret)
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dev_err(adev->dev, "FB failed to set tiling flags\n");
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}
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ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
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if (ret) {
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amdgpu_bo_unreserve(abo);
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goto out_unref;
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}
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ret = amdgpu_bo_kmap(abo, NULL);
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amdgpu_bo_unreserve(abo);
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if (ret) {
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goto out_unref;
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}
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*gobj_p = gobj;
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return 0;
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out_unref:
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amdgpufb_destroy_pinned_object(gobj);
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*gobj_p = NULL;
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return ret;
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}
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static int amdgpufb_create(struct drm_fb_helper *helper,
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struct drm_fb_helper_surface_size *sizes)
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{
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struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
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struct amdgpu_device *adev = rfbdev->adev;
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struct fb_info *info;
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struct drm_framebuffer *fb = NULL;
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struct drm_mode_fb_cmd2 mode_cmd;
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struct drm_gem_object *gobj = NULL;
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struct amdgpu_bo *abo = NULL;
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int ret;
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unsigned long tmp;
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mode_cmd.width = sizes->surface_width;
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mode_cmd.height = sizes->surface_height;
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if (sizes->surface_bpp == 24)
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sizes->surface_bpp = 32;
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mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
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sizes->surface_depth);
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ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
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if (ret) {
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DRM_ERROR("failed to create fbcon object %d\n", ret);
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return ret;
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}
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abo = gem_to_amdgpu_bo(gobj);
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/* okay we have an object now allocate the framebuffer */
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info = drm_fb_helper_alloc_fbi(helper);
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if (IS_ERR(info)) {
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ret = PTR_ERR(info);
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goto out;
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}
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info->par = rfbdev;
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info->skip_vt_switch = true;
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ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
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if (ret) {
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DRM_ERROR("failed to initialize framebuffer %d\n", ret);
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goto out;
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}
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fb = &rfbdev->rfb.base;
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/* setup helper */
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rfbdev->helper.fb = fb;
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strcpy(info->fix.id, "amdgpudrmfb");
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drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
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info->fbops = &amdgpufb_ops;
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tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start;
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info->fix.smem_start = adev->mc.aper_base + tmp;
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info->fix.smem_len = amdgpu_bo_size(abo);
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info->screen_base = amdgpu_bo_kptr(abo);
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info->screen_size = amdgpu_bo_size(abo);
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drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
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/* setup aperture base/size for vesafb takeover */
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info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
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info->apertures->ranges[0].size = adev->mc.aper_size;
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/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
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if (info->screen_base == NULL) {
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ret = -ENOSPC;
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goto out;
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}
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DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
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DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base);
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DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
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DRM_INFO("fb depth is %d\n", fb->format->depth);
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DRM_INFO(" pitch is %d\n", fb->pitches[0]);
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vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
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return 0;
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out:
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if (abo) {
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}
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if (fb && ret) {
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drm_gem_object_put_unlocked(gobj);
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drm_framebuffer_unregister_private(fb);
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drm_framebuffer_cleanup(fb);
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kfree(fb);
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}
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return ret;
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}
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void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
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{
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if (adev->mode_info.rfbdev)
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drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
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}
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static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
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{
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struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
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drm_fb_helper_unregister_fbi(&rfbdev->helper);
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if (rfb->obj) {
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amdgpufb_destroy_pinned_object(rfb->obj);
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rfb->obj = NULL;
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}
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drm_fb_helper_fini(&rfbdev->helper);
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drm_framebuffer_unregister_private(&rfb->base);
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drm_framebuffer_cleanup(&rfb->base);
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return 0;
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}
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static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
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.fb_probe = amdgpufb_create,
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};
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int amdgpu_fbdev_init(struct amdgpu_device *adev)
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{
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struct amdgpu_fbdev *rfbdev;
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int bpp_sel = 32;
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int ret;
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/* don't init fbdev on hw without DCE */
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if (!adev->mode_info.mode_config_initialized)
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return 0;
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/* don't init fbdev if there are no connectors */
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if (list_empty(&adev->ddev->mode_config.connector_list))
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return 0;
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/* select 8 bpp console on low vram cards */
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if (adev->mc.real_vram_size <= (32*1024*1024))
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bpp_sel = 8;
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rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
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if (!rfbdev)
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return -ENOMEM;
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rfbdev->adev = adev;
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adev->mode_info.rfbdev = rfbdev;
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drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
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&amdgpu_fb_helper_funcs);
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ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
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AMDGPUFB_CONN_LIMIT);
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if (ret) {
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kfree(rfbdev);
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return ret;
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}
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drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
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/* disable all the possible outputs/crtcs before entering KMS mode */
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drm_helper_disable_unused_functions(adev->ddev);
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drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
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return 0;
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}
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void amdgpu_fbdev_fini(struct amdgpu_device *adev)
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{
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if (!adev->mode_info.rfbdev)
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return;
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amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
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kfree(adev->mode_info.rfbdev);
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adev->mode_info.rfbdev = NULL;
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}
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void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
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{
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if (adev->mode_info.rfbdev)
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drm_fb_helper_set_suspend(&adev->mode_info.rfbdev->helper,
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state);
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}
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int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
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{
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struct amdgpu_bo *robj;
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int size = 0;
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if (!adev->mode_info.rfbdev)
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return 0;
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robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
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size += amdgpu_bo_size(robj);
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return size;
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}
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bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
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{
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if (!adev->mode_info.rfbdev)
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return false;
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if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
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return true;
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return false;
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}
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void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
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{
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struct amdgpu_fbdev *afbdev;
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struct drm_fb_helper *fb_helper;
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int ret;
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if (!adev)
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return;
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afbdev = adev->mode_info.rfbdev;
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if (!afbdev)
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return;
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fb_helper = &afbdev->helper;
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ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
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if (ret)
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DRM_DEBUG("failed to restore crtc mode\n");
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}
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