mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 13:05:08 +07:00
1d4605e0af
There are no clocks, resets or gpios referenced by Tegra ACPI device so don't access clocks, resets or gpios interface with ACPI device. Clocks, resets and GPIOs for ACPI devices will be handled via ACPI interface. Signed-off-by: Ajay Gupta <ajayg@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
523 lines
12 KiB
C
523 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Synopsys DWC Ethernet Quality-of-Service v4.10a linux driver
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*
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* Copyright (C) 2016 Joao Pinto <jpinto@synopsys.com>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/gpio/consumer.h>
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#include <linux/ethtool.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_net.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/stmmac.h>
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#include "stmmac_platform.h"
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#include "dwmac4.h"
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struct tegra_eqos {
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struct device *dev;
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void __iomem *regs;
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struct reset_control *rst;
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struct clk *clk_master;
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struct clk *clk_slave;
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struct clk *clk_tx;
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struct clk *clk_rx;
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struct gpio_desc *reset;
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};
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static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
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struct plat_stmmacenet_data *plat_dat)
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{
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struct device *dev = &pdev->dev;
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u32 burst_map = 0;
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u32 bit_index = 0;
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u32 a_index = 0;
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if (!plat_dat->axi) {
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plat_dat->axi = kzalloc(sizeof(struct stmmac_axi), GFP_KERNEL);
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if (!plat_dat->axi)
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return -ENOMEM;
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}
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plat_dat->axi->axi_lpi_en = device_property_read_bool(dev,
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"snps,en-lpi");
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if (device_property_read_u32(dev, "snps,write-requests",
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&plat_dat->axi->axi_wr_osr_lmt)) {
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/**
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* Since the register has a reset value of 1, if property
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* is missing, default to 1.
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*/
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plat_dat->axi->axi_wr_osr_lmt = 1;
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} else {
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/**
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* If property exists, to keep the behavior from dwc_eth_qos,
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* subtract one after parsing.
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*/
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plat_dat->axi->axi_wr_osr_lmt--;
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}
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if (device_property_read_u32(dev, "snps,read-requests",
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&plat_dat->axi->axi_rd_osr_lmt)) {
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/**
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* Since the register has a reset value of 1, if property
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* is missing, default to 1.
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*/
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plat_dat->axi->axi_rd_osr_lmt = 1;
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} else {
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/**
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* If property exists, to keep the behavior from dwc_eth_qos,
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* subtract one after parsing.
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*/
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plat_dat->axi->axi_rd_osr_lmt--;
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}
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device_property_read_u32(dev, "snps,burst-map", &burst_map);
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/* converts burst-map bitmask to burst array */
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for (bit_index = 0; bit_index < 7; bit_index++) {
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if (burst_map & (1 << bit_index)) {
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switch (bit_index) {
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case 0:
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plat_dat->axi->axi_blen[a_index] = 4; break;
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case 1:
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plat_dat->axi->axi_blen[a_index] = 8; break;
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case 2:
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plat_dat->axi->axi_blen[a_index] = 16; break;
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case 3:
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plat_dat->axi->axi_blen[a_index] = 32; break;
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case 4:
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plat_dat->axi->axi_blen[a_index] = 64; break;
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case 5:
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plat_dat->axi->axi_blen[a_index] = 128; break;
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case 6:
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plat_dat->axi->axi_blen[a_index] = 256; break;
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default:
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break;
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}
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a_index++;
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}
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}
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/* dwc-qos needs GMAC4, AAL, TSO and PMT */
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plat_dat->has_gmac4 = 1;
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plat_dat->dma_cfg->aal = 1;
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plat_dat->tso_en = 1;
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plat_dat->pmt = 1;
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return 0;
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}
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static void *dwc_qos_probe(struct platform_device *pdev,
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struct plat_stmmacenet_data *plat_dat,
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struct stmmac_resources *stmmac_res)
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{
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int err;
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plat_dat->stmmac_clk = devm_clk_get(&pdev->dev, "apb_pclk");
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if (IS_ERR(plat_dat->stmmac_clk)) {
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dev_err(&pdev->dev, "apb_pclk clock not found.\n");
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return ERR_CAST(plat_dat->stmmac_clk);
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}
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err = clk_prepare_enable(plat_dat->stmmac_clk);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to enable apb_pclk clock: %d\n",
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err);
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return ERR_PTR(err);
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}
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plat_dat->pclk = devm_clk_get(&pdev->dev, "phy_ref_clk");
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if (IS_ERR(plat_dat->pclk)) {
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dev_err(&pdev->dev, "phy_ref_clk clock not found.\n");
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err = PTR_ERR(plat_dat->pclk);
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goto disable;
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}
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err = clk_prepare_enable(plat_dat->pclk);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to enable phy_ref clock: %d\n",
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err);
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goto disable;
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}
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return NULL;
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disable:
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clk_disable_unprepare(plat_dat->stmmac_clk);
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return ERR_PTR(err);
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}
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static int dwc_qos_remove(struct platform_device *pdev)
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{
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struct net_device *ndev = platform_get_drvdata(pdev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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clk_disable_unprepare(priv->plat->pclk);
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clk_disable_unprepare(priv->plat->stmmac_clk);
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return 0;
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}
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#define SDMEMCOMPPADCTRL 0x8800
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#define SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
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#define AUTO_CAL_CONFIG 0x8804
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#define AUTO_CAL_CONFIG_START BIT(31)
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#define AUTO_CAL_CONFIG_ENABLE BIT(29)
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#define AUTO_CAL_STATUS 0x880c
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#define AUTO_CAL_STATUS_ACTIVE BIT(31)
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static void tegra_eqos_fix_speed(void *priv, unsigned int speed)
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{
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struct tegra_eqos *eqos = priv;
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unsigned long rate = 125000000;
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bool needs_calibration = false;
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u32 value;
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int err;
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switch (speed) {
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case SPEED_1000:
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needs_calibration = true;
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rate = 125000000;
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break;
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case SPEED_100:
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needs_calibration = true;
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rate = 25000000;
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break;
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case SPEED_10:
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rate = 2500000;
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break;
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default:
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dev_err(eqos->dev, "invalid speed %u\n", speed);
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break;
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}
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if (needs_calibration) {
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/* calibrate */
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value = readl(eqos->regs + SDMEMCOMPPADCTRL);
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value |= SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD;
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writel(value, eqos->regs + SDMEMCOMPPADCTRL);
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udelay(1);
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value = readl(eqos->regs + AUTO_CAL_CONFIG);
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value |= AUTO_CAL_CONFIG_START | AUTO_CAL_CONFIG_ENABLE;
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writel(value, eqos->regs + AUTO_CAL_CONFIG);
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err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS,
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value,
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value & AUTO_CAL_STATUS_ACTIVE,
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1, 10);
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if (err < 0) {
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dev_err(eqos->dev, "calibration did not start\n");
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goto failed;
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}
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err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS,
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value,
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(value & AUTO_CAL_STATUS_ACTIVE) == 0,
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20, 200);
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if (err < 0) {
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dev_err(eqos->dev, "calibration didn't finish\n");
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goto failed;
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}
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failed:
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value = readl(eqos->regs + SDMEMCOMPPADCTRL);
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value &= ~SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD;
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writel(value, eqos->regs + SDMEMCOMPPADCTRL);
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} else {
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value = readl(eqos->regs + AUTO_CAL_CONFIG);
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value &= ~AUTO_CAL_CONFIG_ENABLE;
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writel(value, eqos->regs + AUTO_CAL_CONFIG);
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}
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err = clk_set_rate(eqos->clk_tx, rate);
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if (err < 0)
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dev_err(eqos->dev, "failed to set TX rate: %d\n", err);
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}
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static int tegra_eqos_init(struct platform_device *pdev, void *priv)
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{
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struct tegra_eqos *eqos = priv;
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unsigned long rate;
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u32 value;
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rate = clk_get_rate(eqos->clk_slave);
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value = (rate / 1000000) - 1;
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writel(value, eqos->regs + GMAC_1US_TIC_COUNTER);
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return 0;
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}
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static void *tegra_eqos_probe(struct platform_device *pdev,
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struct plat_stmmacenet_data *data,
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struct stmmac_resources *res)
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{
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struct device *dev = &pdev->dev;
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struct tegra_eqos *eqos;
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int err;
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eqos = devm_kzalloc(&pdev->dev, sizeof(*eqos), GFP_KERNEL);
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if (!eqos) {
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err = -ENOMEM;
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goto error;
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}
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eqos->dev = &pdev->dev;
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eqos->regs = res->addr;
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if (!is_of_node(dev->fwnode))
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goto bypass_clk_reset_gpio;
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eqos->clk_master = devm_clk_get(&pdev->dev, "master_bus");
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if (IS_ERR(eqos->clk_master)) {
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err = PTR_ERR(eqos->clk_master);
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goto error;
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}
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err = clk_prepare_enable(eqos->clk_master);
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if (err < 0)
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goto error;
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eqos->clk_slave = devm_clk_get(&pdev->dev, "slave_bus");
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if (IS_ERR(eqos->clk_slave)) {
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err = PTR_ERR(eqos->clk_slave);
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goto disable_master;
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}
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data->stmmac_clk = eqos->clk_slave;
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err = clk_prepare_enable(eqos->clk_slave);
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if (err < 0)
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goto disable_master;
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eqos->clk_rx = devm_clk_get(&pdev->dev, "rx");
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if (IS_ERR(eqos->clk_rx)) {
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err = PTR_ERR(eqos->clk_rx);
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goto disable_slave;
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}
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err = clk_prepare_enable(eqos->clk_rx);
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if (err < 0)
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goto disable_slave;
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eqos->clk_tx = devm_clk_get(&pdev->dev, "tx");
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if (IS_ERR(eqos->clk_tx)) {
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err = PTR_ERR(eqos->clk_tx);
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goto disable_rx;
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}
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err = clk_prepare_enable(eqos->clk_tx);
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if (err < 0)
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goto disable_rx;
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eqos->reset = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_OUT_HIGH);
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if (IS_ERR(eqos->reset)) {
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err = PTR_ERR(eqos->reset);
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goto disable_tx;
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}
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usleep_range(2000, 4000);
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gpiod_set_value(eqos->reset, 0);
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/* MDIO bus was already reset just above */
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data->mdio_bus_data->needs_reset = false;
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eqos->rst = devm_reset_control_get(&pdev->dev, "eqos");
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if (IS_ERR(eqos->rst)) {
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err = PTR_ERR(eqos->rst);
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goto reset_phy;
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}
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err = reset_control_assert(eqos->rst);
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if (err < 0)
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goto reset_phy;
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usleep_range(2000, 4000);
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err = reset_control_deassert(eqos->rst);
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if (err < 0)
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goto reset_phy;
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usleep_range(2000, 4000);
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bypass_clk_reset_gpio:
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data->fix_mac_speed = tegra_eqos_fix_speed;
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data->init = tegra_eqos_init;
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data->bsp_priv = eqos;
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err = tegra_eqos_init(pdev, eqos);
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if (err < 0)
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goto reset;
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out:
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return eqos;
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reset:
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reset_control_assert(eqos->rst);
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reset_phy:
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gpiod_set_value(eqos->reset, 1);
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disable_tx:
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clk_disable_unprepare(eqos->clk_tx);
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disable_rx:
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clk_disable_unprepare(eqos->clk_rx);
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disable_slave:
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clk_disable_unprepare(eqos->clk_slave);
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disable_master:
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clk_disable_unprepare(eqos->clk_master);
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error:
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eqos = ERR_PTR(err);
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goto out;
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}
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static int tegra_eqos_remove(struct platform_device *pdev)
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{
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struct tegra_eqos *eqos = get_stmmac_bsp_priv(&pdev->dev);
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reset_control_assert(eqos->rst);
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gpiod_set_value(eqos->reset, 1);
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clk_disable_unprepare(eqos->clk_tx);
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clk_disable_unprepare(eqos->clk_rx);
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clk_disable_unprepare(eqos->clk_slave);
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clk_disable_unprepare(eqos->clk_master);
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return 0;
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}
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struct dwc_eth_dwmac_data {
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void *(*probe)(struct platform_device *pdev,
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struct plat_stmmacenet_data *data,
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struct stmmac_resources *res);
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int (*remove)(struct platform_device *pdev);
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};
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static const struct dwc_eth_dwmac_data dwc_qos_data = {
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.probe = dwc_qos_probe,
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.remove = dwc_qos_remove,
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};
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static const struct dwc_eth_dwmac_data tegra_eqos_data = {
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.probe = tegra_eqos_probe,
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.remove = tegra_eqos_remove,
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};
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static int dwc_eth_dwmac_probe(struct platform_device *pdev)
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{
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const struct dwc_eth_dwmac_data *data;
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struct plat_stmmacenet_data *plat_dat;
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struct stmmac_resources stmmac_res;
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void *priv;
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int ret;
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data = device_get_match_data(&pdev->dev);
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memset(&stmmac_res, 0, sizeof(struct stmmac_resources));
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/**
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* Since stmmac_platform supports name IRQ only, basic platform
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* resource initialization is done in the glue logic.
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*/
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stmmac_res.irq = platform_get_irq(pdev, 0);
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if (stmmac_res.irq < 0)
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return stmmac_res.irq;
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stmmac_res.wol_irq = stmmac_res.irq;
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stmmac_res.addr = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(stmmac_res.addr))
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return PTR_ERR(stmmac_res.addr);
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plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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priv = data->probe(pdev, plat_dat, &stmmac_res);
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if (IS_ERR(priv)) {
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ret = PTR_ERR(priv);
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if (ret != -EPROBE_DEFER)
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dev_err(&pdev->dev, "failed to probe subdriver: %d\n",
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ret);
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goto remove_config;
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}
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ret = dwc_eth_dwmac_config_dt(pdev, plat_dat);
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if (ret)
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goto remove;
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ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
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if (ret)
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goto remove;
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return ret;
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remove:
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data->remove(pdev);
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remove_config:
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stmmac_remove_config_dt(pdev, plat_dat);
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return ret;
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}
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static int dwc_eth_dwmac_remove(struct platform_device *pdev)
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{
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struct net_device *ndev = platform_get_drvdata(pdev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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const struct dwc_eth_dwmac_data *data;
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int err;
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data = device_get_match_data(&pdev->dev);
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err = stmmac_dvr_remove(&pdev->dev);
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if (err < 0)
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dev_err(&pdev->dev, "failed to remove platform: %d\n", err);
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err = data->remove(pdev);
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if (err < 0)
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dev_err(&pdev->dev, "failed to remove subdriver: %d\n", err);
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stmmac_remove_config_dt(pdev, priv->plat);
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return err;
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}
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static const struct of_device_id dwc_eth_dwmac_match[] = {
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{ .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data },
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{ .compatible = "nvidia,tegra186-eqos", .data = &tegra_eqos_data },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
|
|
|
|
static struct platform_driver dwc_eth_dwmac_driver = {
|
|
.probe = dwc_eth_dwmac_probe,
|
|
.remove = dwc_eth_dwmac_remove,
|
|
.driver = {
|
|
.name = "dwc-eth-dwmac",
|
|
.pm = &stmmac_pltfr_pm_ops,
|
|
.of_match_table = dwc_eth_dwmac_match,
|
|
},
|
|
};
|
|
module_platform_driver(dwc_eth_dwmac_driver);
|
|
|
|
MODULE_AUTHOR("Joao Pinto <jpinto@synopsys.com>");
|
|
MODULE_DESCRIPTION("Synopsys DWC Ethernet Quality-of-Service v4.10a driver");
|
|
MODULE_LICENSE("GPL v2");
|