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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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73346794b4
The A31 is a quad Cortex-A7. Add the logic to use the IPs used to control the CPU configuration and the CPU power so that we can bring up secondary CPUs at boot. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
125 lines
3.3 KiB
C
125 lines
3.3 KiB
C
/*
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* SMP support for Allwinner SoCs
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*
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* Copyright (C) 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* Based on code
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* Copyright (C) 2012-2013 Allwinner Ltd.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/memory.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include "common.h"
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#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
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#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
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#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
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#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08)
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#define CPUCFG_GEN_CTRL_REG 0x184
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#define CPUCFG_PRIVATE0_REG 0x1a4
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#define CPUCFG_PRIVATE1_REG 0x1a8
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#define CPUCFG_DBG_CTL0_REG 0x1e0
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#define CPUCFG_DBG_CTL1_REG 0x1e4
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#define PRCM_CPU_PWROFF_REG 0x100
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#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140)
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static void __iomem *cpucfg_membase;
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static void __iomem *prcm_membase;
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static DEFINE_SPINLOCK(cpu_lock);
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static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *node;
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node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
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if (!node) {
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pr_err("Missing A31 PRCM node in the device tree\n");
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return;
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}
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prcm_membase = of_iomap(node, 0);
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if (!prcm_membase) {
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pr_err("Couldn't map A31 PRCM registers\n");
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return;
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}
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node = of_find_compatible_node(NULL, NULL,
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"allwinner,sun6i-a31-cpuconfig");
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if (!node) {
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pr_err("Missing A31 CPU config node in the device tree\n");
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return;
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}
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cpucfg_membase = of_iomap(node, 0);
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if (!cpucfg_membase)
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pr_err("Couldn't map A31 CPU config registers\n");
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}
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static int sun6i_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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u32 reg;
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int i;
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if (!(prcm_membase && cpucfg_membase))
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return -EFAULT;
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spin_lock(&cpu_lock);
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/* Set CPU boot address */
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writel(virt_to_phys(sun6i_secondary_startup),
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cpucfg_membase + CPUCFG_PRIVATE0_REG);
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/* Assert the CPU core in reset */
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writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
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/* Assert the L1 cache in reset */
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reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
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writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
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/* Disable external debug access */
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reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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/* Power up the CPU */
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for (i = 0; i <= 8; i++)
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writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
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mdelay(10);
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/* Clear CPU power-off gating */
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reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
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writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
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mdelay(1);
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/* Deassert the CPU core reset */
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writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
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/* Enable back the external debug accesses */
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reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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spin_unlock(&cpu_lock);
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return 0;
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}
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struct smp_operations sun6i_smp_ops __initdata = {
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.smp_prepare_cpus = sun6i_smp_prepare_cpus,
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.smp_boot_secondary = sun6i_smp_boot_secondary,
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};
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