When looking at this driver for a client, I noticed the code that
configures the HSYNC pulse clobbers the display width in the same
register. It only preserves the MS part of the width in bit 3 and zeros
the LS part of the width in bits 9 to 4. This doesn't matter during
initialization as the width is configured afterwards, but subsequent use
of the FBIPUT_HSYNC ioctl would clobber the width.
Preserve bits 9 to 0 of LCD_RASTER_TIMING_0_REG when configuring the
horizontal sync.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
