mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 14:26:41 +07:00
9301975ec2
This merges branches irq/genirq, irq/sparseirq-v4, timers/hpet-percpu and x86/uv. The sparseirq branch is just preliminary groundwork: no sparse IRQs are actually implemented by this tree anymore - just the new APIs are added while keeping the old way intact as well (the new APIs map 1:1 to irq_desc[]). The 'real' sparse IRQ support will then be a relatively small patch ontop of this - with a v2.6.29 merge target. * 'genirq-v28-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (178 commits) genirq: improve include files intr_remapping: fix typo io_apic: make irq_mis_count available on 64-bit too genirq: fix name space collisions of nr_irqs in arch/* genirq: fix name space collision of nr_irqs in autoprobe.c genirq: use iterators for irq_desc loops proc: fixup irq iterator genirq: add reverse iterator for irq_desc x86: move ack_bad_irq() to irq.c x86: unify show_interrupts() and proc helpers x86: cleanup show_interrupts genirq: cleanup the sparseirq modifications genirq: remove artifacts from sparseirq removal genirq: revert dynarray genirq: remove irq_to_desc_alloc genirq: remove sparse irq code genirq: use inline function for irq_to_desc genirq: consolidate nr_irqs and for_each_irq_desc() x86: remove sparse irq from Kconfig genirq: define nr_irqs for architectures with GENERIC_HARDIRQS=n ...
1523 lines
40 KiB
C
1523 lines
40 KiB
C
/*
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* Freescale QUICC Engine UART device driver
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* Copyright 2007 Freescale Semiconductor, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* This driver adds support for UART devices via Freescale's QUICC Engine
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* found on some Freescale SOCs.
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*
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* If Soft-UART support is needed but not already present, then this driver
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* will request and upload the "Soft-UART" microcode upon probe. The
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* filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
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* is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
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* (e.g. "11" for 1.1).
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*/
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#include <linux/module.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <linux/of_platform.h>
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#include <linux/dma-mapping.h>
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#include <linux/fs_uart_pd.h>
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#include <asm/ucc_slow.h>
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#include <linux/firmware.h>
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#include <asm/reg.h>
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/*
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* The GUMR flag for Soft UART. This would normally be defined in qe.h,
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* but Soft-UART is a hack and we want to keep everything related to it in
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* this file.
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*/
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#define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
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/*
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* soft_uart is 1 if we need to use Soft-UART mode
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*/
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static int soft_uart;
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/*
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* firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
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*/
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static int firmware_loaded;
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/* Enable this macro to configure all serial ports in internal loopback
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mode */
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/* #define LOOPBACK */
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/* The major and minor device numbers are defined in
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* http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE
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* UART, we have major number 204 and minor numbers 46 - 49, which are the
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* same as for the CPM2. This decision was made because no Freescale part
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* has both a CPM and a QE.
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*/
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#define SERIAL_QE_MAJOR 204
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#define SERIAL_QE_MINOR 46
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/* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
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#define UCC_MAX_UART 4
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/* The number of buffer descriptors for receiving characters. */
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#define RX_NUM_FIFO 4
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/* The number of buffer descriptors for transmitting characters. */
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#define TX_NUM_FIFO 4
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/* The maximum size of the character buffer for a single RX BD. */
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#define RX_BUF_SIZE 32
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/* The maximum size of the character buffer for a single TX BD. */
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#define TX_BUF_SIZE 32
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/*
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* The number of jiffies to wait after receiving a close command before the
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* device is actually closed. This allows the last few characters to be
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* sent over the wire.
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*/
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#define UCC_WAIT_CLOSING 100
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struct ucc_uart_pram {
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struct ucc_slow_pram common;
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u8 res1[8]; /* reserved */
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__be16 maxidl; /* Maximum idle chars */
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__be16 idlc; /* temp idle counter */
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__be16 brkcr; /* Break count register */
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__be16 parec; /* receive parity error counter */
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__be16 frmec; /* receive framing error counter */
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__be16 nosec; /* receive noise counter */
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__be16 brkec; /* receive break condition counter */
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__be16 brkln; /* last received break length */
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__be16 uaddr[2]; /* UART address character 1 & 2 */
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__be16 rtemp; /* Temp storage */
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__be16 toseq; /* Transmit out of sequence char */
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__be16 cchars[8]; /* control characters 1-8 */
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__be16 rccm; /* receive control character mask */
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__be16 rccr; /* receive control character register */
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__be16 rlbc; /* receive last break character */
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__be16 res2; /* reserved */
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__be32 res3; /* reserved, should be cleared */
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u8 res4; /* reserved, should be cleared */
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u8 res5[3]; /* reserved, should be cleared */
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__be32 res6; /* reserved, should be cleared */
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__be32 res7; /* reserved, should be cleared */
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__be32 res8; /* reserved, should be cleared */
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__be32 res9; /* reserved, should be cleared */
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__be32 res10; /* reserved, should be cleared */
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__be32 res11; /* reserved, should be cleared */
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__be32 res12; /* reserved, should be cleared */
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__be32 res13; /* reserved, should be cleared */
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/* The rest is for Soft-UART only */
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__be16 supsmr; /* 0x90, Shadow UPSMR */
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__be16 res92; /* 0x92, reserved, initialize to 0 */
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__be32 rx_state; /* 0x94, RX state, initialize to 0 */
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__be32 rx_cnt; /* 0x98, RX count, initialize to 0 */
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u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */
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u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */
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u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */
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u8 res14[0xBC - 0x9F]; /* reserved */
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__be32 dump_ptr; /* 0xBC, Dump pointer */
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__be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */
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u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */
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u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */
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__be16 tx_state; /* 0xC6, TX state */
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u8 res15[0xD0 - 0xC8]; /* reserved */
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__be32 resD0; /* 0xD0, reserved, initialize to 0 */
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u8 resD4; /* 0xD4, reserved, initialize to 0 */
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__be16 resD5; /* 0xD5, reserved, initialize to 0 */
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} __attribute__ ((packed));
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/* SUPSMR definitions, for Soft-UART only */
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#define UCC_UART_SUPSMR_SL 0x8000
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#define UCC_UART_SUPSMR_RPM_MASK 0x6000
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#define UCC_UART_SUPSMR_RPM_ODD 0x0000
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#define UCC_UART_SUPSMR_RPM_LOW 0x2000
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#define UCC_UART_SUPSMR_RPM_EVEN 0x4000
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#define UCC_UART_SUPSMR_RPM_HIGH 0x6000
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#define UCC_UART_SUPSMR_PEN 0x1000
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#define UCC_UART_SUPSMR_TPM_MASK 0x0C00
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#define UCC_UART_SUPSMR_TPM_ODD 0x0000
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#define UCC_UART_SUPSMR_TPM_LOW 0x0400
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#define UCC_UART_SUPSMR_TPM_EVEN 0x0800
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#define UCC_UART_SUPSMR_TPM_HIGH 0x0C00
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#define UCC_UART_SUPSMR_FRZ 0x0100
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#define UCC_UART_SUPSMR_UM_MASK 0x00c0
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#define UCC_UART_SUPSMR_UM_NORMAL 0x0000
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#define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040
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#define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0
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#define UCC_UART_SUPSMR_CL_MASK 0x0030
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#define UCC_UART_SUPSMR_CL_8 0x0030
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#define UCC_UART_SUPSMR_CL_7 0x0020
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#define UCC_UART_SUPSMR_CL_6 0x0010
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#define UCC_UART_SUPSMR_CL_5 0x0000
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#define UCC_UART_TX_STATE_AHDLC 0x00
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#define UCC_UART_TX_STATE_UART 0x01
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#define UCC_UART_TX_STATE_X1 0x00
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#define UCC_UART_TX_STATE_X16 0x80
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#define UCC_UART_PRAM_ALIGNMENT 0x100
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#define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD
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#define NUM_CONTROL_CHARS 8
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/* Private per-port data structure */
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struct uart_qe_port {
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struct uart_port port;
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struct ucc_slow __iomem *uccp;
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struct ucc_uart_pram __iomem *uccup;
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struct ucc_slow_info us_info;
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struct ucc_slow_private *us_private;
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struct device_node *np;
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unsigned int ucc_num; /* First ucc is 0, not 1 */
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u16 rx_nrfifos;
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u16 rx_fifosize;
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u16 tx_nrfifos;
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u16 tx_fifosize;
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int wait_closing;
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u32 flags;
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struct qe_bd *rx_bd_base;
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struct qe_bd *rx_cur;
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struct qe_bd *tx_bd_base;
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struct qe_bd *tx_cur;
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unsigned char *tx_buf;
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unsigned char *rx_buf;
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void *bd_virt; /* virtual address of the BD buffers */
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dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
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unsigned int bd_size; /* size of BD buffer space */
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};
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static struct uart_driver ucc_uart_driver = {
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.owner = THIS_MODULE,
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.driver_name = "ucc_uart",
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.dev_name = "ttyQE",
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.major = SERIAL_QE_MAJOR,
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.minor = SERIAL_QE_MINOR,
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.nr = UCC_MAX_UART,
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};
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/*
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* Virtual to physical address translation.
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*
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* Given the virtual address for a character buffer, this function returns
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* the physical (DMA) equivalent.
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*/
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static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
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{
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if (likely((addr >= qe_port->bd_virt)) &&
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(addr < (qe_port->bd_virt + qe_port->bd_size)))
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return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
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/* something nasty happened */
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printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
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BUG();
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return 0;
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}
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/*
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* Physical to virtual address translation.
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*
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* Given the physical (DMA) address for a character buffer, this function
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* returns the virtual equivalent.
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*/
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static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
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{
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/* sanity check */
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if (likely((addr >= qe_port->bd_dma_addr) &&
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(addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
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return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
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/* something nasty happened */
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printk(KERN_ERR "%s: addr=%x\n", __func__, addr);
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BUG();
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return NULL;
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}
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/*
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* Return 1 if the QE is done transmitting all buffers for this port
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*
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* This function scans each BD in sequence. If we find a BD that is not
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* ready (READY=1), then we return 0 indicating that the QE is still sending
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* data. If we reach the last BD (WRAP=1), then we know we've scanned
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* the entire list, and all BDs are done.
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*/
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static unsigned int qe_uart_tx_empty(struct uart_port *port)
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{
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struct uart_qe_port *qe_port =
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container_of(port, struct uart_qe_port, port);
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struct qe_bd *bdp = qe_port->tx_bd_base;
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while (1) {
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if (in_be16(&bdp->status) & BD_SC_READY)
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/* This BD is not done, so return "not done" */
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return 0;
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if (in_be16(&bdp->status) & BD_SC_WRAP)
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/*
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* This BD is done and it's the last one, so return
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* "done"
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*/
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return 1;
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bdp++;
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};
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}
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/*
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* Set the modem control lines
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*
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* Although the QE can control the modem control lines (e.g. CTS), we
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* don't need that support. This function must exist, however, otherwise
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* the kernel will panic.
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*/
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void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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}
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/*
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* Get the current modem control line status
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*
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* Although the QE can control the modem control lines (e.g. CTS), this
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* driver currently doesn't support that, so we always return Carrier
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* Detect, Data Set Ready, and Clear To Send.
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*/
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static unsigned int qe_uart_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
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}
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/*
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* Disable the transmit interrupt.
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*
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* Although this function is called "stop_tx", it does not actually stop
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* transmission of data. Instead, it tells the QE to not generate an
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* interrupt when the UCC is finished sending characters.
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*/
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static void qe_uart_stop_tx(struct uart_port *port)
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{
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struct uart_qe_port *qe_port =
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container_of(port, struct uart_qe_port, port);
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clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
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}
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/*
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* Transmit as many characters to the HW as possible.
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*
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* This function will attempt to stuff of all the characters from the
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* kernel's transmit buffer into TX BDs.
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*
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* A return value of non-zero indicates that it sucessfully stuffed all
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* characters from the kernel buffer.
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*
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* A return value of zero indicates that there are still characters in the
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* kernel's buffer that have not been transmitted, but there are no more BDs
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* available. This function should be called again after a BD has been made
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* available.
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*/
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static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
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{
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struct qe_bd *bdp;
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unsigned char *p;
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unsigned int count;
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struct uart_port *port = &qe_port->port;
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struct circ_buf *xmit = &port->info->xmit;
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bdp = qe_port->rx_cur;
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/* Handle xon/xoff */
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if (port->x_char) {
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/* Pick next descriptor and fill from buffer */
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bdp = qe_port->tx_cur;
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p = qe2cpu_addr(bdp->buf, qe_port);
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*p++ = port->x_char;
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out_be16(&bdp->length, 1);
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setbits16(&bdp->status, BD_SC_READY);
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/* Get next BD. */
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if (in_be16(&bdp->status) & BD_SC_WRAP)
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bdp = qe_port->tx_bd_base;
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else
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bdp++;
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qe_port->tx_cur = bdp;
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port->icount.tx++;
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port->x_char = 0;
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return 1;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
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qe_uart_stop_tx(port);
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return 0;
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}
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/* Pick next descriptor and fill from buffer */
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bdp = qe_port->tx_cur;
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while (!(in_be16(&bdp->status) & BD_SC_READY) &&
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(xmit->tail != xmit->head)) {
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count = 0;
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p = qe2cpu_addr(bdp->buf, qe_port);
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while (count < qe_port->tx_fifosize) {
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*p++ = xmit->buf[xmit->tail];
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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count++;
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if (xmit->head == xmit->tail)
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break;
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}
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out_be16(&bdp->length, count);
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setbits16(&bdp->status, BD_SC_READY);
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/* Get next BD. */
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if (in_be16(&bdp->status) & BD_SC_WRAP)
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bdp = qe_port->tx_bd_base;
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else
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bdp++;
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}
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qe_port->tx_cur = bdp;
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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if (uart_circ_empty(xmit)) {
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/* The kernel buffer is empty, so turn off TX interrupts. We
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don't need to be told when the QE is finished transmitting
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the data. */
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qe_uart_stop_tx(port);
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return 0;
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}
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return 1;
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}
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|
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/*
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* Start transmitting data
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*
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* This function will start transmitting any available data, if the port
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* isn't already transmitting data.
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*/
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static void qe_uart_start_tx(struct uart_port *port)
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{
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struct uart_qe_port *qe_port =
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container_of(port, struct uart_qe_port, port);
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|
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/* If we currently are transmitting, then just return */
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if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
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return;
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/* Otherwise, pump the port and start transmission */
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if (qe_uart_tx_pump(qe_port))
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setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
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}
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|
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/*
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* Stop transmitting data
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*/
|
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static void qe_uart_stop_rx(struct uart_port *port)
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{
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struct uart_qe_port *qe_port =
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container_of(port, struct uart_qe_port, port);
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|
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clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
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}
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|
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/*
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* Enable status change interrupts
|
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*
|
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* We don't support status change interrupts, but we need to define this
|
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* function otherwise the kernel will panic.
|
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*/
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static void qe_uart_enable_ms(struct uart_port *port)
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{
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}
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|
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/* Start or stop sending break signal
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*
|
|
* This function controls the sending of a break signal. If break_state=1,
|
|
* then we start sending a break signal. If break_state=0, then we stop
|
|
* sending the break signal.
|
|
*/
|
|
static void qe_uart_break_ctl(struct uart_port *port, int break_state)
|
|
{
|
|
struct uart_qe_port *qe_port =
|
|
container_of(port, struct uart_qe_port, port);
|
|
|
|
if (break_state)
|
|
ucc_slow_stop_tx(qe_port->us_private);
|
|
else
|
|
ucc_slow_restart_tx(qe_port->us_private);
|
|
}
|
|
|
|
/* ISR helper function for receiving character.
|
|
*
|
|
* This function is called by the ISR to handling receiving characters
|
|
*/
|
|
static void qe_uart_int_rx(struct uart_qe_port *qe_port)
|
|
{
|
|
int i;
|
|
unsigned char ch, *cp;
|
|
struct uart_port *port = &qe_port->port;
|
|
struct tty_struct *tty = port->info->port.tty;
|
|
struct qe_bd *bdp;
|
|
u16 status;
|
|
unsigned int flg;
|
|
|
|
/* Just loop through the closed BDs and copy the characters into
|
|
* the buffer.
|
|
*/
|
|
bdp = qe_port->rx_cur;
|
|
while (1) {
|
|
status = in_be16(&bdp->status);
|
|
|
|
/* If this one is empty, then we assume we've read them all */
|
|
if (status & BD_SC_EMPTY)
|
|
break;
|
|
|
|
/* get number of characters, and check space in RX buffer */
|
|
i = in_be16(&bdp->length);
|
|
|
|
/* If we don't have enough room in RX buffer for the entire BD,
|
|
* then we try later, which will be the next RX interrupt.
|
|
*/
|
|
if (tty_buffer_request_room(tty, i) < i) {
|
|
dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
|
|
return;
|
|
}
|
|
|
|
/* get pointer */
|
|
cp = qe2cpu_addr(bdp->buf, qe_port);
|
|
|
|
/* loop through the buffer */
|
|
while (i-- > 0) {
|
|
ch = *cp++;
|
|
port->icount.rx++;
|
|
flg = TTY_NORMAL;
|
|
|
|
if (!i && status &
|
|
(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
|
|
goto handle_error;
|
|
if (uart_handle_sysrq_char(port, ch))
|
|
continue;
|
|
|
|
error_return:
|
|
tty_insert_flip_char(tty, ch, flg);
|
|
|
|
}
|
|
|
|
/* This BD is ready to be used again. Clear status. get next */
|
|
clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
|
|
BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
|
|
if (in_be16(&bdp->status) & BD_SC_WRAP)
|
|
bdp = qe_port->rx_bd_base;
|
|
else
|
|
bdp++;
|
|
|
|
}
|
|
|
|
/* Write back buffer pointer */
|
|
qe_port->rx_cur = bdp;
|
|
|
|
/* Activate BH processing */
|
|
tty_flip_buffer_push(tty);
|
|
|
|
return;
|
|
|
|
/* Error processing */
|
|
|
|
handle_error:
|
|
/* Statistics */
|
|
if (status & BD_SC_BR)
|
|
port->icount.brk++;
|
|
if (status & BD_SC_PR)
|
|
port->icount.parity++;
|
|
if (status & BD_SC_FR)
|
|
port->icount.frame++;
|
|
if (status & BD_SC_OV)
|
|
port->icount.overrun++;
|
|
|
|
/* Mask out ignored conditions */
|
|
status &= port->read_status_mask;
|
|
|
|
/* Handle the remaining ones */
|
|
if (status & BD_SC_BR)
|
|
flg = TTY_BREAK;
|
|
else if (status & BD_SC_PR)
|
|
flg = TTY_PARITY;
|
|
else if (status & BD_SC_FR)
|
|
flg = TTY_FRAME;
|
|
|
|
/* Overrun does not affect the current character ! */
|
|
if (status & BD_SC_OV)
|
|
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
|
|
#ifdef SUPPORT_SYSRQ
|
|
port->sysrq = 0;
|
|
#endif
|
|
goto error_return;
|
|
}
|
|
|
|
/* Interrupt handler
|
|
*
|
|
* This interrupt handler is called after a BD is processed.
|
|
*/
|
|
static irqreturn_t qe_uart_int(int irq, void *data)
|
|
{
|
|
struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
|
|
struct ucc_slow __iomem *uccp = qe_port->uccp;
|
|
u16 events;
|
|
|
|
/* Clear the interrupts */
|
|
events = in_be16(&uccp->ucce);
|
|
out_be16(&uccp->ucce, events);
|
|
|
|
if (events & UCC_UART_UCCE_BRKE)
|
|
uart_handle_break(&qe_port->port);
|
|
|
|
if (events & UCC_UART_UCCE_RX)
|
|
qe_uart_int_rx(qe_port);
|
|
|
|
if (events & UCC_UART_UCCE_TX)
|
|
qe_uart_tx_pump(qe_port);
|
|
|
|
return events ? IRQ_HANDLED : IRQ_NONE;
|
|
}
|
|
|
|
/* Initialize buffer descriptors
|
|
*
|
|
* This function initializes all of the RX and TX buffer descriptors.
|
|
*/
|
|
static void qe_uart_initbd(struct uart_qe_port *qe_port)
|
|
{
|
|
int i;
|
|
void *bd_virt;
|
|
struct qe_bd *bdp;
|
|
|
|
/* Set the physical address of the host memory buffers in the buffer
|
|
* descriptors, and the virtual address for us to work with.
|
|
*/
|
|
bd_virt = qe_port->bd_virt;
|
|
bdp = qe_port->rx_bd_base;
|
|
qe_port->rx_cur = qe_port->rx_bd_base;
|
|
for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
|
|
out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
|
|
out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
|
|
out_be16(&bdp->length, 0);
|
|
bd_virt += qe_port->rx_fifosize;
|
|
bdp++;
|
|
}
|
|
|
|
/* */
|
|
out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
|
|
out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
|
|
out_be16(&bdp->length, 0);
|
|
|
|
/* Set the physical address of the host memory
|
|
* buffers in the buffer descriptors, and the
|
|
* virtual address for us to work with.
|
|
*/
|
|
bd_virt = qe_port->bd_virt +
|
|
L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
|
|
qe_port->tx_cur = qe_port->tx_bd_base;
|
|
bdp = qe_port->tx_bd_base;
|
|
for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
|
|
out_be16(&bdp->status, BD_SC_INTRPT);
|
|
out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
|
|
out_be16(&bdp->length, 0);
|
|
bd_virt += qe_port->tx_fifosize;
|
|
bdp++;
|
|
}
|
|
|
|
/* Loopback requires the preamble bit to be set on the first TX BD */
|
|
#ifdef LOOPBACK
|
|
setbits16(&qe_port->tx_cur->status, BD_SC_P);
|
|
#endif
|
|
|
|
out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
|
|
out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
|
|
out_be16(&bdp->length, 0);
|
|
}
|
|
|
|
/*
|
|
* Initialize a UCC for UART.
|
|
*
|
|
* This function configures a given UCC to be used as a UART device. Basic
|
|
* UCC initialization is handled in qe_uart_request_port(). This function
|
|
* does all the UART-specific stuff.
|
|
*/
|
|
static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
|
|
{
|
|
u32 cecr_subblock;
|
|
struct ucc_slow __iomem *uccp = qe_port->uccp;
|
|
struct ucc_uart_pram *uccup = qe_port->uccup;
|
|
|
|
unsigned int i;
|
|
|
|
/* First, disable TX and RX in the UCC */
|
|
ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
|
|
|
|
/* Program the UCC UART parameter RAM */
|
|
out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
|
|
out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
|
|
out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
|
|
out_be16(&uccup->maxidl, 0x10);
|
|
out_be16(&uccup->brkcr, 1);
|
|
out_be16(&uccup->parec, 0);
|
|
out_be16(&uccup->frmec, 0);
|
|
out_be16(&uccup->nosec, 0);
|
|
out_be16(&uccup->brkec, 0);
|
|
out_be16(&uccup->uaddr[0], 0);
|
|
out_be16(&uccup->uaddr[1], 0);
|
|
out_be16(&uccup->toseq, 0);
|
|
for (i = 0; i < 8; i++)
|
|
out_be16(&uccup->cchars[i], 0xC000);
|
|
out_be16(&uccup->rccm, 0xc0ff);
|
|
|
|
/* Configure the GUMR registers for UART */
|
|
if (soft_uart)
|
|
/* Soft-UART requires a 1X multiplier for TX */
|
|
clrsetbits_be32(&uccp->gumr_l,
|
|
UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
|
|
UCC_SLOW_GUMR_L_RDCR_MASK,
|
|
UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
|
|
UCC_SLOW_GUMR_L_RDCR_16);
|
|
else
|
|
clrsetbits_be32(&uccp->gumr_l,
|
|
UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
|
|
UCC_SLOW_GUMR_L_RDCR_MASK,
|
|
UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
|
|
UCC_SLOW_GUMR_L_RDCR_16);
|
|
|
|
clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
|
|
UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
|
|
|
|
#ifdef LOOPBACK
|
|
clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
|
|
UCC_SLOW_GUMR_L_DIAG_LOOP);
|
|
clrsetbits_be32(&uccp->gumr_h,
|
|
UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
|
|
UCC_SLOW_GUMR_H_CDS);
|
|
#endif
|
|
|
|
/* Enable rx interrupts and clear all pending events. */
|
|
out_be16(&uccp->uccm, 0);
|
|
out_be16(&uccp->ucce, 0xffff);
|
|
out_be16(&uccp->udsr, 0x7e7e);
|
|
|
|
/* Initialize UPSMR */
|
|
out_be16(&uccp->upsmr, 0);
|
|
|
|
if (soft_uart) {
|
|
out_be16(&uccup->supsmr, 0x30);
|
|
out_be16(&uccup->res92, 0);
|
|
out_be32(&uccup->rx_state, 0);
|
|
out_be32(&uccup->rx_cnt, 0);
|
|
out_8(&uccup->rx_bitmark, 0);
|
|
out_8(&uccup->rx_length, 10);
|
|
out_be32(&uccup->dump_ptr, 0x4000);
|
|
out_8(&uccup->rx_temp_dlst_qe, 0);
|
|
out_be32(&uccup->rx_frame_rem, 0);
|
|
out_8(&uccup->rx_frame_rem_size, 0);
|
|
/* Soft-UART requires TX to be 1X */
|
|
out_8(&uccup->tx_mode,
|
|
UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
|
|
out_be16(&uccup->tx_state, 0);
|
|
out_8(&uccup->resD4, 0);
|
|
out_be16(&uccup->resD5, 0);
|
|
|
|
/* Set UART mode.
|
|
* Enable receive and transmit.
|
|
*/
|
|
|
|
/* From the microcode errata:
|
|
* 1.GUMR_L register, set mode=0010 (QMC).
|
|
* 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
|
|
* 3.Set GUMR_H[19:20] (Transparent mode)
|
|
* 4.Clear GUMR_H[26] (RFW)
|
|
* ...
|
|
* 6.Receiver must use 16x over sampling
|
|
*/
|
|
clrsetbits_be32(&uccp->gumr_l,
|
|
UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
|
|
UCC_SLOW_GUMR_L_RDCR_MASK,
|
|
UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
|
|
UCC_SLOW_GUMR_L_RDCR_16);
|
|
|
|
clrsetbits_be32(&uccp->gumr_h,
|
|
UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
|
|
UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
|
|
UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
|
|
|
|
#ifdef LOOPBACK
|
|
clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
|
|
UCC_SLOW_GUMR_L_DIAG_LOOP);
|
|
clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
|
|
UCC_SLOW_GUMR_H_CDS);
|
|
#endif
|
|
|
|
cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
|
|
qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
|
|
QE_CR_PROTOCOL_UNSPECIFIED, 0);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Initialize the port.
|
|
*/
|
|
static int qe_uart_startup(struct uart_port *port)
|
|
{
|
|
struct uart_qe_port *qe_port =
|
|
container_of(port, struct uart_qe_port, port);
|
|
int ret;
|
|
|
|
/*
|
|
* If we're using Soft-UART mode, then we need to make sure the
|
|
* firmware has been uploaded first.
|
|
*/
|
|
if (soft_uart && !firmware_loaded) {
|
|
dev_err(port->dev, "Soft-UART firmware not uploaded\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
qe_uart_initbd(qe_port);
|
|
qe_uart_init_ucc(qe_port);
|
|
|
|
/* Install interrupt handler. */
|
|
ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
|
|
qe_port);
|
|
if (ret) {
|
|
dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
|
|
return ret;
|
|
}
|
|
|
|
/* Startup rx-int */
|
|
setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
|
|
ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Shutdown the port.
|
|
*/
|
|
static void qe_uart_shutdown(struct uart_port *port)
|
|
{
|
|
struct uart_qe_port *qe_port =
|
|
container_of(port, struct uart_qe_port, port);
|
|
struct ucc_slow __iomem *uccp = qe_port->uccp;
|
|
unsigned int timeout = 20;
|
|
|
|
/* Disable RX and TX */
|
|
|
|
/* Wait for all the BDs marked sent */
|
|
while (!qe_uart_tx_empty(port)) {
|
|
if (!--timeout) {
|
|
dev_warn(port->dev, "shutdown timeout\n");
|
|
break;
|
|
}
|
|
set_current_state(TASK_UNINTERRUPTIBLE);
|
|
schedule_timeout(2);
|
|
}
|
|
|
|
if (qe_port->wait_closing) {
|
|
/* Wait a bit longer */
|
|
set_current_state(TASK_UNINTERRUPTIBLE);
|
|
schedule_timeout(qe_port->wait_closing);
|
|
}
|
|
|
|
/* Stop uarts */
|
|
ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
|
|
clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
|
|
|
|
/* Shut them really down and reinit buffer descriptors */
|
|
ucc_slow_graceful_stop_tx(qe_port->us_private);
|
|
qe_uart_initbd(qe_port);
|
|
|
|
free_irq(port->irq, qe_port);
|
|
}
|
|
|
|
/*
|
|
* Set the serial port parameters.
|
|
*/
|
|
static void qe_uart_set_termios(struct uart_port *port,
|
|
struct ktermios *termios, struct ktermios *old)
|
|
{
|
|
struct uart_qe_port *qe_port =
|
|
container_of(port, struct uart_qe_port, port);
|
|
struct ucc_slow __iomem *uccp = qe_port->uccp;
|
|
unsigned int baud;
|
|
unsigned long flags;
|
|
u16 upsmr = in_be16(&uccp->upsmr);
|
|
struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
|
|
u16 supsmr = in_be16(&uccup->supsmr);
|
|
u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
|
|
|
|
/* Character length programmed into the mode register is the
|
|
* sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
|
|
* 1 or 2 stop bits, minus 1.
|
|
* The value 'bits' counts this for us.
|
|
*/
|
|
|
|
/* byte size */
|
|
upsmr &= UCC_UART_UPSMR_CL_MASK;
|
|
supsmr &= UCC_UART_SUPSMR_CL_MASK;
|
|
|
|
switch (termios->c_cflag & CSIZE) {
|
|
case CS5:
|
|
upsmr |= UCC_UART_UPSMR_CL_5;
|
|
supsmr |= UCC_UART_SUPSMR_CL_5;
|
|
char_length += 5;
|
|
break;
|
|
case CS6:
|
|
upsmr |= UCC_UART_UPSMR_CL_6;
|
|
supsmr |= UCC_UART_SUPSMR_CL_6;
|
|
char_length += 6;
|
|
break;
|
|
case CS7:
|
|
upsmr |= UCC_UART_UPSMR_CL_7;
|
|
supsmr |= UCC_UART_SUPSMR_CL_7;
|
|
char_length += 7;
|
|
break;
|
|
default: /* case CS8 */
|
|
upsmr |= UCC_UART_UPSMR_CL_8;
|
|
supsmr |= UCC_UART_SUPSMR_CL_8;
|
|
char_length += 8;
|
|
break;
|
|
}
|
|
|
|
/* If CSTOPB is set, we want two stop bits */
|
|
if (termios->c_cflag & CSTOPB) {
|
|
upsmr |= UCC_UART_UPSMR_SL;
|
|
supsmr |= UCC_UART_SUPSMR_SL;
|
|
char_length++; /* + SL */
|
|
}
|
|
|
|
if (termios->c_cflag & PARENB) {
|
|
upsmr |= UCC_UART_UPSMR_PEN;
|
|
supsmr |= UCC_UART_SUPSMR_PEN;
|
|
char_length++; /* + PEN */
|
|
|
|
if (!(termios->c_cflag & PARODD)) {
|
|
upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
|
|
UCC_UART_UPSMR_TPM_MASK);
|
|
upsmr |= UCC_UART_UPSMR_RPM_EVEN |
|
|
UCC_UART_UPSMR_TPM_EVEN;
|
|
supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
|
|
UCC_UART_SUPSMR_TPM_MASK);
|
|
supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
|
|
UCC_UART_SUPSMR_TPM_EVEN;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Set up parity check flag
|
|
*/
|
|
port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
|
|
if (termios->c_iflag & INPCK)
|
|
port->read_status_mask |= BD_SC_FR | BD_SC_PR;
|
|
if (termios->c_iflag & (BRKINT | PARMRK))
|
|
port->read_status_mask |= BD_SC_BR;
|
|
|
|
/*
|
|
* Characters to ignore
|
|
*/
|
|
port->ignore_status_mask = 0;
|
|
if (termios->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
|
|
if (termios->c_iflag & IGNBRK) {
|
|
port->ignore_status_mask |= BD_SC_BR;
|
|
/*
|
|
* If we're ignore parity and break indicators, ignore
|
|
* overruns too. (For real raw support).
|
|
*/
|
|
if (termios->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |= BD_SC_OV;
|
|
}
|
|
/*
|
|
* !!! ignore all characters if CREAD is not set
|
|
*/
|
|
if ((termios->c_cflag & CREAD) == 0)
|
|
port->read_status_mask &= ~BD_SC_EMPTY;
|
|
|
|
baud = uart_get_baud_rate(port, termios, old, 0, 115200);
|
|
|
|
/* Do we really need a spinlock here? */
|
|
spin_lock_irqsave(&port->lock, flags);
|
|
|
|
out_be16(&uccp->upsmr, upsmr);
|
|
if (soft_uart) {
|
|
out_be16(&uccup->supsmr, supsmr);
|
|
out_8(&uccup->rx_length, char_length);
|
|
|
|
/* Soft-UART requires a 1X multiplier for TX */
|
|
qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
|
|
qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
|
|
} else {
|
|
qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
|
|
qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
}
|
|
|
|
/*
|
|
* Return a pointer to a string that describes what kind of port this is.
|
|
*/
|
|
static const char *qe_uart_type(struct uart_port *port)
|
|
{
|
|
return "QE";
|
|
}
|
|
|
|
/*
|
|
* Allocate any memory and I/O resources required by the port.
|
|
*/
|
|
static int qe_uart_request_port(struct uart_port *port)
|
|
{
|
|
int ret;
|
|
struct uart_qe_port *qe_port =
|
|
container_of(port, struct uart_qe_port, port);
|
|
struct ucc_slow_info *us_info = &qe_port->us_info;
|
|
struct ucc_slow_private *uccs;
|
|
unsigned int rx_size, tx_size;
|
|
void *bd_virt;
|
|
dma_addr_t bd_dma_addr = 0;
|
|
|
|
ret = ucc_slow_init(us_info, &uccs);
|
|
if (ret) {
|
|
dev_err(port->dev, "could not initialize UCC%u\n",
|
|
qe_port->ucc_num);
|
|
return ret;
|
|
}
|
|
|
|
qe_port->us_private = uccs;
|
|
qe_port->uccp = uccs->us_regs;
|
|
qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
|
|
qe_port->rx_bd_base = uccs->rx_bd;
|
|
qe_port->tx_bd_base = uccs->tx_bd;
|
|
|
|
/*
|
|
* Allocate the transmit and receive data buffers.
|
|
*/
|
|
|
|
rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
|
|
tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
|
|
|
|
bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
|
|
GFP_KERNEL);
|
|
if (!bd_virt) {
|
|
dev_err(port->dev, "could not allocate buffer descriptors\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
qe_port->bd_virt = bd_virt;
|
|
qe_port->bd_dma_addr = bd_dma_addr;
|
|
qe_port->bd_size = rx_size + tx_size;
|
|
|
|
qe_port->rx_buf = bd_virt;
|
|
qe_port->tx_buf = qe_port->rx_buf + rx_size;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Configure the port.
|
|
*
|
|
* We say we're a CPM-type port because that's mostly true. Once the device
|
|
* is configured, this driver operates almost identically to the CPM serial
|
|
* driver.
|
|
*/
|
|
static void qe_uart_config_port(struct uart_port *port, int flags)
|
|
{
|
|
if (flags & UART_CONFIG_TYPE) {
|
|
port->type = PORT_CPM;
|
|
qe_uart_request_port(port);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Release any memory and I/O resources that were allocated in
|
|
* qe_uart_request_port().
|
|
*/
|
|
static void qe_uart_release_port(struct uart_port *port)
|
|
{
|
|
struct uart_qe_port *qe_port =
|
|
container_of(port, struct uart_qe_port, port);
|
|
struct ucc_slow_private *uccs = qe_port->us_private;
|
|
|
|
dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
|
|
qe_port->bd_dma_addr);
|
|
|
|
ucc_slow_free(uccs);
|
|
}
|
|
|
|
/*
|
|
* Verify that the data in serial_struct is suitable for this device.
|
|
*/
|
|
static int qe_uart_verify_port(struct uart_port *port,
|
|
struct serial_struct *ser)
|
|
{
|
|
if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
|
|
return -EINVAL;
|
|
|
|
if (ser->irq < 0 || ser->irq >= nr_irqs)
|
|
return -EINVAL;
|
|
|
|
if (ser->baud_base < 9600)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
/* UART operations
|
|
*
|
|
* Details on these functions can be found in Documentation/serial/driver
|
|
*/
|
|
static struct uart_ops qe_uart_pops = {
|
|
.tx_empty = qe_uart_tx_empty,
|
|
.set_mctrl = qe_uart_set_mctrl,
|
|
.get_mctrl = qe_uart_get_mctrl,
|
|
.stop_tx = qe_uart_stop_tx,
|
|
.start_tx = qe_uart_start_tx,
|
|
.stop_rx = qe_uart_stop_rx,
|
|
.enable_ms = qe_uart_enable_ms,
|
|
.break_ctl = qe_uart_break_ctl,
|
|
.startup = qe_uart_startup,
|
|
.shutdown = qe_uart_shutdown,
|
|
.set_termios = qe_uart_set_termios,
|
|
.type = qe_uart_type,
|
|
.release_port = qe_uart_release_port,
|
|
.request_port = qe_uart_request_port,
|
|
.config_port = qe_uart_config_port,
|
|
.verify_port = qe_uart_verify_port,
|
|
};
|
|
|
|
/*
|
|
* Obtain the SOC model number and revision level
|
|
*
|
|
* This function parses the device tree to obtain the SOC model. It then
|
|
* reads the SVR register to the revision.
|
|
*
|
|
* The device tree stores the SOC model two different ways.
|
|
*
|
|
* The new way is:
|
|
*
|
|
* cpu@0 {
|
|
* compatible = "PowerPC,8323";
|
|
* device_type = "cpu";
|
|
* ...
|
|
*
|
|
*
|
|
* The old way is:
|
|
* PowerPC,8323@0 {
|
|
* device_type = "cpu";
|
|
* ...
|
|
*
|
|
* This code first checks the new way, and then the old way.
|
|
*/
|
|
static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
|
|
{
|
|
struct device_node *np;
|
|
const char *soc_string;
|
|
unsigned int svr;
|
|
unsigned int soc;
|
|
|
|
/* Find the CPU node */
|
|
np = of_find_node_by_type(NULL, "cpu");
|
|
if (!np)
|
|
return 0;
|
|
/* Find the compatible property */
|
|
soc_string = of_get_property(np, "compatible", NULL);
|
|
if (!soc_string)
|
|
/* No compatible property, so try the name. */
|
|
soc_string = np->name;
|
|
|
|
/* Extract the SOC number from the "PowerPC," string */
|
|
if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
|
|
return 0;
|
|
|
|
/* Get the revision from the SVR */
|
|
svr = mfspr(SPRN_SVR);
|
|
*rev_h = (svr >> 4) & 0xf;
|
|
*rev_l = svr & 0xf;
|
|
|
|
return soc;
|
|
}
|
|
|
|
/*
|
|
* requst_firmware_nowait() callback function
|
|
*
|
|
* This function is called by the kernel when a firmware is made available,
|
|
* or if it times out waiting for the firmware.
|
|
*/
|
|
static void uart_firmware_cont(const struct firmware *fw, void *context)
|
|
{
|
|
struct qe_firmware *firmware;
|
|
struct device *dev = context;
|
|
int ret;
|
|
|
|
if (!fw) {
|
|
dev_err(dev, "firmware not found\n");
|
|
return;
|
|
}
|
|
|
|
firmware = (struct qe_firmware *) fw->data;
|
|
|
|
if (firmware->header.length != fw->size) {
|
|
dev_err(dev, "invalid firmware\n");
|
|
return;
|
|
}
|
|
|
|
ret = qe_upload_firmware(firmware);
|
|
if (ret) {
|
|
dev_err(dev, "could not load firmware\n");
|
|
return;
|
|
}
|
|
|
|
firmware_loaded = 1;
|
|
}
|
|
|
|
static int ucc_uart_probe(struct of_device *ofdev,
|
|
const struct of_device_id *match)
|
|
{
|
|
struct device_node *np = ofdev->node;
|
|
const unsigned int *iprop; /* Integer OF properties */
|
|
const char *sprop; /* String OF properties */
|
|
struct uart_qe_port *qe_port = NULL;
|
|
struct resource res;
|
|
int ret;
|
|
|
|
/*
|
|
* Determine if we need Soft-UART mode
|
|
*/
|
|
if (of_find_property(np, "soft-uart", NULL)) {
|
|
dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
|
|
soft_uart = 1;
|
|
}
|
|
|
|
/*
|
|
* If we are using Soft-UART, determine if we need to upload the
|
|
* firmware, too.
|
|
*/
|
|
if (soft_uart) {
|
|
struct qe_firmware_info *qe_fw_info;
|
|
|
|
qe_fw_info = qe_get_firmware_info();
|
|
|
|
/* Check if the firmware has been uploaded. */
|
|
if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
|
|
firmware_loaded = 1;
|
|
} else {
|
|
char filename[32];
|
|
unsigned int soc;
|
|
unsigned int rev_h;
|
|
unsigned int rev_l;
|
|
|
|
soc = soc_info(&rev_h, &rev_l);
|
|
if (!soc) {
|
|
dev_err(&ofdev->dev, "unknown CPU model\n");
|
|
return -ENXIO;
|
|
}
|
|
sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
|
|
soc, rev_h, rev_l);
|
|
|
|
dev_info(&ofdev->dev, "waiting for firmware %s\n",
|
|
filename);
|
|
|
|
/*
|
|
* We call request_firmware_nowait instead of
|
|
* request_firmware so that the driver can load and
|
|
* initialize the ports without holding up the rest of
|
|
* the kernel. If hotplug support is enabled in the
|
|
* kernel, then we use it.
|
|
*/
|
|
ret = request_firmware_nowait(THIS_MODULE,
|
|
FW_ACTION_HOTPLUG, filename, &ofdev->dev,
|
|
&ofdev->dev, uart_firmware_cont);
|
|
if (ret) {
|
|
dev_err(&ofdev->dev,
|
|
"could not load firmware %s\n",
|
|
filename);
|
|
return ret;
|
|
}
|
|
}
|
|
}
|
|
|
|
qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
|
|
if (!qe_port) {
|
|
dev_err(&ofdev->dev, "can't allocate QE port structure\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Search for IRQ and mapbase */
|
|
ret = of_address_to_resource(np, 0, &res);
|
|
if (ret) {
|
|
dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
|
|
kfree(qe_port);
|
|
return ret;
|
|
}
|
|
if (!res.start) {
|
|
dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
|
|
kfree(qe_port);
|
|
return -EINVAL;
|
|
}
|
|
qe_port->port.mapbase = res.start;
|
|
|
|
/* Get the UCC number (device ID) */
|
|
/* UCCs are numbered 1-7 */
|
|
iprop = of_get_property(np, "cell-index", NULL);
|
|
if (!iprop) {
|
|
iprop = of_get_property(np, "device-id", NULL);
|
|
if (!iprop) {
|
|
dev_err(&ofdev->dev, "UCC is unspecified in "
|
|
"device tree\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
|
|
dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
|
|
kfree(qe_port);
|
|
return -ENODEV;
|
|
}
|
|
qe_port->ucc_num = *iprop - 1;
|
|
|
|
/*
|
|
* In the future, we should not require the BRG to be specified in the
|
|
* device tree. If no clock-source is specified, then just pick a BRG
|
|
* to use. This requires a new QE library function that manages BRG
|
|
* assignments.
|
|
*/
|
|
|
|
sprop = of_get_property(np, "rx-clock-name", NULL);
|
|
if (!sprop) {
|
|
dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
|
|
kfree(qe_port);
|
|
return -ENODEV;
|
|
}
|
|
|
|
qe_port->us_info.rx_clock = qe_clock_source(sprop);
|
|
if ((qe_port->us_info.rx_clock < QE_BRG1) ||
|
|
(qe_port->us_info.rx_clock > QE_BRG16)) {
|
|
dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
|
|
kfree(qe_port);
|
|
return -ENODEV;
|
|
}
|
|
|
|
#ifdef LOOPBACK
|
|
/* In internal loopback mode, TX and RX must use the same clock */
|
|
qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
|
|
#else
|
|
sprop = of_get_property(np, "tx-clock-name", NULL);
|
|
if (!sprop) {
|
|
dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
|
|
kfree(qe_port);
|
|
return -ENODEV;
|
|
}
|
|
qe_port->us_info.tx_clock = qe_clock_source(sprop);
|
|
#endif
|
|
if ((qe_port->us_info.tx_clock < QE_BRG1) ||
|
|
(qe_port->us_info.tx_clock > QE_BRG16)) {
|
|
dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
|
|
kfree(qe_port);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Get the port number, numbered 0-3 */
|
|
iprop = of_get_property(np, "port-number", NULL);
|
|
if (!iprop) {
|
|
dev_err(&ofdev->dev, "missing port-number in device tree\n");
|
|
kfree(qe_port);
|
|
return -EINVAL;
|
|
}
|
|
qe_port->port.line = *iprop;
|
|
if (qe_port->port.line >= UCC_MAX_UART) {
|
|
dev_err(&ofdev->dev, "port-number must be 0-%u\n",
|
|
UCC_MAX_UART - 1);
|
|
kfree(qe_port);
|
|
return -EINVAL;
|
|
}
|
|
|
|
qe_port->port.irq = irq_of_parse_and_map(np, 0);
|
|
if (qe_port->port.irq == NO_IRQ) {
|
|
dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
|
|
qe_port->ucc_num + 1);
|
|
kfree(qe_port);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Newer device trees have an "fsl,qe" compatible property for the QE
|
|
* node, but we still need to support older device trees.
|
|
*/
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,qe");
|
|
if (!np) {
|
|
np = of_find_node_by_type(NULL, "qe");
|
|
if (!np) {
|
|
dev_err(&ofdev->dev, "could not find 'qe' node\n");
|
|
kfree(qe_port);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
iprop = of_get_property(np, "brg-frequency", NULL);
|
|
if (!iprop) {
|
|
dev_err(&ofdev->dev,
|
|
"missing brg-frequency in device tree\n");
|
|
kfree(qe_port);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (*iprop)
|
|
qe_port->port.uartclk = *iprop;
|
|
else {
|
|
/*
|
|
* Older versions of U-Boot do not initialize the brg-frequency
|
|
* property, so in this case we assume the BRG frequency is
|
|
* half the QE bus frequency.
|
|
*/
|
|
iprop = of_get_property(np, "bus-frequency", NULL);
|
|
if (!iprop) {
|
|
dev_err(&ofdev->dev,
|
|
"missing QE bus-frequency in device tree\n");
|
|
kfree(qe_port);
|
|
return -EINVAL;
|
|
}
|
|
if (*iprop)
|
|
qe_port->port.uartclk = *iprop / 2;
|
|
else {
|
|
dev_err(&ofdev->dev,
|
|
"invalid QE bus-frequency in device tree\n");
|
|
kfree(qe_port);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
spin_lock_init(&qe_port->port.lock);
|
|
qe_port->np = np;
|
|
qe_port->port.dev = &ofdev->dev;
|
|
qe_port->port.ops = &qe_uart_pops;
|
|
qe_port->port.iotype = UPIO_MEM;
|
|
|
|
qe_port->tx_nrfifos = TX_NUM_FIFO;
|
|
qe_port->tx_fifosize = TX_BUF_SIZE;
|
|
qe_port->rx_nrfifos = RX_NUM_FIFO;
|
|
qe_port->rx_fifosize = RX_BUF_SIZE;
|
|
|
|
qe_port->wait_closing = UCC_WAIT_CLOSING;
|
|
qe_port->port.fifosize = 512;
|
|
qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
|
|
|
|
qe_port->us_info.ucc_num = qe_port->ucc_num;
|
|
qe_port->us_info.regs = (phys_addr_t) res.start;
|
|
qe_port->us_info.irq = qe_port->port.irq;
|
|
|
|
qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
|
|
qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
|
|
|
|
/* Make sure ucc_slow_init() initializes both TX and RX */
|
|
qe_port->us_info.init_tx = 1;
|
|
qe_port->us_info.init_rx = 1;
|
|
|
|
/* Add the port to the uart sub-system. This will cause
|
|
* qe_uart_config_port() to be called, so the us_info structure must
|
|
* be initialized.
|
|
*/
|
|
ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
|
|
if (ret) {
|
|
dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
|
|
qe_port->port.line);
|
|
kfree(qe_port);
|
|
return ret;
|
|
}
|
|
|
|
dev_set_drvdata(&ofdev->dev, qe_port);
|
|
|
|
dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
|
|
qe_port->ucc_num + 1, qe_port->port.line);
|
|
|
|
/* Display the mknod command for this device */
|
|
dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
|
|
qe_port->port.line, SERIAL_QE_MAJOR,
|
|
SERIAL_QE_MINOR + qe_port->port.line);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ucc_uart_remove(struct of_device *ofdev)
|
|
{
|
|
struct uart_qe_port *qe_port = dev_get_drvdata(&ofdev->dev);
|
|
|
|
dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
|
|
|
|
uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
|
|
|
|
dev_set_drvdata(&ofdev->dev, NULL);
|
|
kfree(qe_port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id ucc_uart_match[] = {
|
|
{
|
|
.type = "serial",
|
|
.compatible = "ucc_uart",
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ucc_uart_match);
|
|
|
|
static struct of_platform_driver ucc_uart_of_driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "ucc_uart",
|
|
.match_table = ucc_uart_match,
|
|
.probe = ucc_uart_probe,
|
|
.remove = ucc_uart_remove,
|
|
};
|
|
|
|
static int __init ucc_uart_init(void)
|
|
{
|
|
int ret;
|
|
|
|
printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
|
|
#ifdef LOOPBACK
|
|
printk(KERN_INFO "ucc-uart: Using loopback mode\n");
|
|
#endif
|
|
|
|
ret = uart_register_driver(&ucc_uart_driver);
|
|
if (ret) {
|
|
printk(KERN_ERR "ucc-uart: could not register UART driver\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_register_platform_driver(&ucc_uart_of_driver);
|
|
if (ret)
|
|
printk(KERN_ERR
|
|
"ucc-uart: could not register platform driver\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit ucc_uart_exit(void)
|
|
{
|
|
printk(KERN_INFO
|
|
"Freescale QUICC Engine UART device driver unloading\n");
|
|
|
|
of_unregister_platform_driver(&ucc_uart_of_driver);
|
|
uart_unregister_driver(&ucc_uart_driver);
|
|
}
|
|
|
|
module_init(ucc_uart_init);
|
|
module_exit(ucc_uart_exit);
|
|
|
|
MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
|
|
MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
|
|
|