mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 09:06:34 +07:00
5694cecdb0
In the end, we ended up with quite a lot more than I expected: - Support for ARMv8.3 Pointer Authentication in userspace (CRIU and kernel-side support to come later) - Support for per-thread stack canaries, pending an update to GCC that is currently undergoing review - Support for kexec_file_load(), which permits secure boot of a kexec payload but also happens to improve the performance of kexec dramatically because we can avoid the sucky purgatory code from userspace. Kdump will come later (requires updates to libfdt). - Optimisation of our dynamic CPU feature framework, so that all detected features are enabled via a single stop_machine() invocation - KPTI whitelisting of Cortex-A CPUs unaffected by Meltdown, so that they can benefit from global TLB entries when KASLR is not in use - 52-bit virtual addressing for userspace (kernel remains 48-bit) - Patch in LSE atomics for per-cpu atomic operations - Custom preempt.h implementation to avoid unconditional calls to preempt_schedule() from preempt_enable() - Support for the new 'SB' Speculation Barrier instruction - Vectorised implementation of XOR checksumming and CRC32 optimisations - Workaround for Cortex-A76 erratum #1165522 - Improved compatibility with Clang/LLD - Support for TX2 system PMUS for profiling the L3 cache and DMC - Reflect read-only permissions in the linear map by default - Ensure MMIO reads are ordered with subsequent calls to Xdelay() - Initial support for memory hotplug - Tweak the threshold when we invalidate the TLB by-ASID, so that mremap() performance is improved for ranges spanning multiple PMDs. - Minor refactoring and cleanups -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJcE4TmAAoJELescNyEwWM0Nr0H/iaU7/wQSzHyNXtZoImyKTul Blu2ga4/EqUrTU7AVVfmkl/3NBILWlgQVpY6tH6EfXQuvnxqD7CizbHyLdyO+z0S B5PsFUH2GLMNAi48AUNqGqkgb2knFbg+T+9IimijDBkKg1G/KhQnRg6bXX32mLJv Une8oshUPBVJMsHN1AcQknzKariuoE3u0SgJ+eOZ9yA2ZwKxP4yy1SkDt3xQrtI0 lojeRjxcyjTP1oGRNZC+BWUtGOT35p7y6cGTnBd/4TlqBGz5wVAJUcdoxnZ6JYVR O8+ob9zU+4I0+SKt80s7pTLqQiL9rxkKZ5joWK1pr1g9e0s5N5yoETXKFHgJYP8= =sYdt -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 festive updates from Will Deacon: "In the end, we ended up with quite a lot more than I expected: - Support for ARMv8.3 Pointer Authentication in userspace (CRIU and kernel-side support to come later) - Support for per-thread stack canaries, pending an update to GCC that is currently undergoing review - Support for kexec_file_load(), which permits secure boot of a kexec payload but also happens to improve the performance of kexec dramatically because we can avoid the sucky purgatory code from userspace. Kdump will come later (requires updates to libfdt). - Optimisation of our dynamic CPU feature framework, so that all detected features are enabled via a single stop_machine() invocation - KPTI whitelisting of Cortex-A CPUs unaffected by Meltdown, so that they can benefit from global TLB entries when KASLR is not in use - 52-bit virtual addressing for userspace (kernel remains 48-bit) - Patch in LSE atomics for per-cpu atomic operations - Custom preempt.h implementation to avoid unconditional calls to preempt_schedule() from preempt_enable() - Support for the new 'SB' Speculation Barrier instruction - Vectorised implementation of XOR checksumming and CRC32 optimisations - Workaround for Cortex-A76 erratum #1165522 - Improved compatibility with Clang/LLD - Support for TX2 system PMUS for profiling the L3 cache and DMC - Reflect read-only permissions in the linear map by default - Ensure MMIO reads are ordered with subsequent calls to Xdelay() - Initial support for memory hotplug - Tweak the threshold when we invalidate the TLB by-ASID, so that mremap() performance is improved for ranges spanning multiple PMDs. - Minor refactoring and cleanups" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (125 commits) arm64: kaslr: print PHYS_OFFSET in dump_kernel_offset() arm64: sysreg: Use _BITUL() when defining register bits arm64: cpufeature: Rework ptr auth hwcaps using multi_entry_cap_matches arm64: cpufeature: Reduce number of pointer auth CPU caps from 6 to 4 arm64: docs: document pointer authentication arm64: ptr auth: Move per-thread keys from thread_info to thread_struct arm64: enable pointer authentication arm64: add prctl control for resetting ptrauth keys arm64: perf: strip PAC when unwinding userspace arm64: expose user PAC bit positions via ptrace arm64: add basic pointer authentication support arm64/cpufeature: detect pointer authentication arm64: Don't trap host pointer auth use to EL2 arm64/kvm: hide ptrauth from guests arm64/kvm: consistently handle host HCR_EL2 flags arm64: add pointer authentication register bits arm64: add comments about EC exception levels arm64: perf: Treat EXCLUDE_EL* bit definitions as unsigned arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field arm64: enable per-task stack canaries ...
745 lines
18 KiB
C
745 lines
18 KiB
C
/*
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* Contains CPU specific errata definitions
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*
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* Copyright (C) 2014 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/arm-smccc.h>
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#include <linux/psci.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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static bool __maybe_unused
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is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
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{
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const struct arm64_midr_revidr *fix;
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u32 midr = read_cpuid_id(), revidr;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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if (!is_midr_in_range(midr, &entry->midr_range))
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return false;
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midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
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revidr = read_cpuid(REVIDR_EL1);
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for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
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if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
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return false;
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return true;
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}
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static bool __maybe_unused
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is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
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}
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static bool __maybe_unused
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is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
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{
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u32 model;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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model = read_cpuid_id();
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model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
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MIDR_ARCHITECTURE_MASK;
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return model == entry->midr_range.model;
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}
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static bool
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has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
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u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
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u64 ctr_raw, ctr_real;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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/*
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* We want to make sure that all the CPUs in the system expose
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* a consistent CTR_EL0 to make sure that applications behaves
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* correctly with migration.
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*
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* If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
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*
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* 1) It is safe if the system doesn't support IDC, as CPU anyway
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* reports IDC = 0, consistent with the rest.
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*
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* 2) If the system has IDC, it is still safe as we trap CTR_EL0
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* access on this CPU via the ARM64_HAS_CACHE_IDC capability.
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*
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* So, we need to make sure either the raw CTR_EL0 or the effective
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* CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
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*/
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ctr_raw = read_cpuid_cachetype() & mask;
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ctr_real = read_cpuid_effective_cachetype() & mask;
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return (ctr_real != sys) && (ctr_raw != sys);
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}
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static void
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cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
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{
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u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
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/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
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if ((read_cpuid_cachetype() & mask) !=
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(arm64_ftr_reg_ctrel0.sys_val & mask))
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
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}
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atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
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#ifdef CONFIG_KVM_INDIRECT_VECTORS
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extern char __smccc_workaround_1_smc_start[];
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extern char __smccc_workaround_1_smc_end[];
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static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
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int i;
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for (i = 0; i < SZ_2K; i += 0x80)
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memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
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__flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
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}
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static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
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const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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static DEFINE_RAW_SPINLOCK(bp_lock);
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int cpu, slot = -1;
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/*
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* enable_smccc_arch_workaround_1() passes NULL for the hyp_vecs
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* start/end if we're a guest. Skip the hyp-vectors work.
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*/
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if (!hyp_vecs_start) {
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__this_cpu_write(bp_hardening_data.fn, fn);
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return;
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}
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raw_spin_lock(&bp_lock);
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for_each_possible_cpu(cpu) {
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if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
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slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
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break;
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}
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}
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if (slot == -1) {
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slot = atomic_inc_return(&arm64_el2_vector_last_slot);
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BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
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__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
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}
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__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
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__this_cpu_write(bp_hardening_data.fn, fn);
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raw_spin_unlock(&bp_lock);
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}
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#else
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#define __smccc_workaround_1_smc_start NULL
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#define __smccc_workaround_1_smc_end NULL
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static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
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const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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__this_cpu_write(bp_hardening_data.fn, fn);
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}
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#endif /* CONFIG_KVM_INDIRECT_VECTORS */
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static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
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bp_hardening_cb_t fn,
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const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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u64 pfr0;
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if (!entry->matches(entry, SCOPE_LOCAL_CPU))
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return;
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pfr0 = read_cpuid(ID_AA64PFR0_EL1);
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if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
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return;
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__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
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}
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#include <uapi/linux/psci.h>
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#include <linux/arm-smccc.h>
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#include <linux/psci.h>
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static void call_smc_arch_workaround_1(void)
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{
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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}
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static void call_hvc_arch_workaround_1(void)
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{
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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}
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static void qcom_link_stack_sanitization(void)
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{
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u64 tmp;
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asm volatile("mov %0, x30 \n"
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".rept 16 \n"
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"bl . + 4 \n"
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".endr \n"
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"mov x30, %0 \n"
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: "=&r" (tmp));
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}
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static void
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enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
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{
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bp_hardening_cb_t cb;
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void *smccc_start, *smccc_end;
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struct arm_smccc_res res;
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u32 midr = read_cpuid_id();
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if (!entry->matches(entry, SCOPE_LOCAL_CPU))
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return;
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if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
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return;
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switch (psci_ops.conduit) {
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case PSCI_CONDUIT_HVC:
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_1, &res);
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if ((int)res.a0 < 0)
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return;
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cb = call_hvc_arch_workaround_1;
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/* This is a guest, no need to patch KVM vectors */
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smccc_start = NULL;
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smccc_end = NULL;
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break;
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case PSCI_CONDUIT_SMC:
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_1, &res);
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if ((int)res.a0 < 0)
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return;
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cb = call_smc_arch_workaround_1;
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smccc_start = __smccc_workaround_1_smc_start;
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smccc_end = __smccc_workaround_1_smc_end;
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break;
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default:
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return;
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}
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if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
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((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
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cb = qcom_link_stack_sanitization;
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install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
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return;
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}
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
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#ifdef CONFIG_ARM64_SSBD
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DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
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int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
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static const struct ssbd_options {
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const char *str;
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int state;
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} ssbd_options[] = {
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{ "force-on", ARM64_SSBD_FORCE_ENABLE, },
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{ "force-off", ARM64_SSBD_FORCE_DISABLE, },
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{ "kernel", ARM64_SSBD_KERNEL, },
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};
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static int __init ssbd_cfg(char *buf)
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{
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int i;
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if (!buf || !buf[0])
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(ssbd_options); i++) {
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int len = strlen(ssbd_options[i].str);
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if (strncmp(buf, ssbd_options[i].str, len))
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continue;
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ssbd_state = ssbd_options[i].state;
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return 0;
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}
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return -EINVAL;
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}
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early_param("ssbd", ssbd_cfg);
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void __init arm64_update_smccc_conduit(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr,
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int nr_inst)
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{
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u32 insn;
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BUG_ON(nr_inst != 1);
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switch (psci_ops.conduit) {
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case PSCI_CONDUIT_HVC:
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insn = aarch64_insn_get_hvc_value();
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break;
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case PSCI_CONDUIT_SMC:
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insn = aarch64_insn_get_smc_value();
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break;
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default:
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return;
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}
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*updptr = cpu_to_le32(insn);
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}
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void __init arm64_enable_wa2_handling(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr,
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int nr_inst)
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{
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BUG_ON(nr_inst != 1);
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/*
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* Only allow mitigation on EL1 entry/exit and guest
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* ARCH_WORKAROUND_2 handling if the SSBD state allows it to
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* be flipped.
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*/
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if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL)
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*updptr = cpu_to_le32(aarch64_insn_gen_nop());
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}
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void arm64_set_ssbd_mitigation(bool state)
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{
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if (this_cpu_has_cap(ARM64_SSBS)) {
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if (state)
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asm volatile(SET_PSTATE_SSBS(0));
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else
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asm volatile(SET_PSTATE_SSBS(1));
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return;
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}
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switch (psci_ops.conduit) {
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case PSCI_CONDUIT_HVC:
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
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break;
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case PSCI_CONDUIT_SMC:
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
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break;
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default:
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WARN_ON_ONCE(1);
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break;
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}
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}
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static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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struct arm_smccc_res res;
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bool required = true;
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s32 val;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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if (this_cpu_has_cap(ARM64_SSBS)) {
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required = false;
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goto out_printmsg;
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}
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if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
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ssbd_state = ARM64_SSBD_UNKNOWN;
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return false;
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}
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switch (psci_ops.conduit) {
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case PSCI_CONDUIT_HVC:
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_2, &res);
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break;
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case PSCI_CONDUIT_SMC:
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_2, &res);
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break;
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default:
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ssbd_state = ARM64_SSBD_UNKNOWN;
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return false;
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}
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val = (s32)res.a0;
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|
|
|
switch (val) {
|
|
case SMCCC_RET_NOT_SUPPORTED:
|
|
ssbd_state = ARM64_SSBD_UNKNOWN;
|
|
return false;
|
|
|
|
case SMCCC_RET_NOT_REQUIRED:
|
|
pr_info_once("%s mitigation not required\n", entry->desc);
|
|
ssbd_state = ARM64_SSBD_MITIGATED;
|
|
return false;
|
|
|
|
case SMCCC_RET_SUCCESS:
|
|
required = true;
|
|
break;
|
|
|
|
case 1: /* Mitigation not required on this CPU */
|
|
required = false;
|
|
break;
|
|
|
|
default:
|
|
WARN_ON(1);
|
|
return false;
|
|
}
|
|
|
|
switch (ssbd_state) {
|
|
case ARM64_SSBD_FORCE_DISABLE:
|
|
arm64_set_ssbd_mitigation(false);
|
|
required = false;
|
|
break;
|
|
|
|
case ARM64_SSBD_KERNEL:
|
|
if (required) {
|
|
__this_cpu_write(arm64_ssbd_callback_required, 1);
|
|
arm64_set_ssbd_mitigation(true);
|
|
}
|
|
break;
|
|
|
|
case ARM64_SSBD_FORCE_ENABLE:
|
|
arm64_set_ssbd_mitigation(true);
|
|
required = true;
|
|
break;
|
|
|
|
default:
|
|
WARN_ON(1);
|
|
break;
|
|
}
|
|
|
|
out_printmsg:
|
|
switch (ssbd_state) {
|
|
case ARM64_SSBD_FORCE_DISABLE:
|
|
pr_info_once("%s disabled from command-line\n", entry->desc);
|
|
break;
|
|
|
|
case ARM64_SSBD_FORCE_ENABLE:
|
|
pr_info_once("%s forced from command-line\n", entry->desc);
|
|
break;
|
|
}
|
|
|
|
return required;
|
|
}
|
|
#endif /* CONFIG_ARM64_SSBD */
|
|
|
|
static void __maybe_unused
|
|
cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
|
|
{
|
|
sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
|
|
}
|
|
|
|
#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
|
|
.matches = is_affected_midr_range, \
|
|
.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
|
|
|
|
#define CAP_MIDR_ALL_VERSIONS(model) \
|
|
.matches = is_affected_midr_range, \
|
|
.midr_range = MIDR_ALL_VERSIONS(model)
|
|
|
|
#define MIDR_FIXED(rev, revidr_mask) \
|
|
.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
|
|
|
|
#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
|
|
CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
|
|
|
|
#define CAP_MIDR_RANGE_LIST(list) \
|
|
.matches = is_affected_midr_range_list, \
|
|
.midr_range_list = list
|
|
|
|
/* Errata affecting a range of revisions of given model variant */
|
|
#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
|
|
ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
|
|
|
|
/* Errata affecting a single variant/revision of a model */
|
|
#define ERRATA_MIDR_REV(model, var, rev) \
|
|
ERRATA_MIDR_RANGE(model, var, rev, var, rev)
|
|
|
|
/* Errata affecting all variants/revisions of a given a model */
|
|
#define ERRATA_MIDR_ALL_VERSIONS(model) \
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
|
|
CAP_MIDR_ALL_VERSIONS(model)
|
|
|
|
/* Errata affecting a list of midr ranges, with same work around */
|
|
#define ERRATA_MIDR_RANGE_LIST(midr_list) \
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
|
|
CAP_MIDR_RANGE_LIST(midr_list)
|
|
|
|
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
|
|
|
|
/*
|
|
* List of CPUs where we need to issue a psci call to
|
|
* harden the branch predictor.
|
|
*/
|
|
static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
|
|
MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
|
|
MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
|
|
MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
|
|
MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
|
|
MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER),
|
|
{},
|
|
};
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_HARDEN_EL2_VECTORS
|
|
|
|
static const struct midr_range arm64_harden_el2_vectors[] = {
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
|
|
{},
|
|
};
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
|
|
|
|
static const struct midr_range arm64_repeat_tlbi_cpus[] = {
|
|
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
|
|
MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0),
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1286807
|
|
MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
|
|
#endif
|
|
{},
|
|
};
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_27456
|
|
static const struct midr_range cavium_erratum_27456_cpus[] = {
|
|
/* Cavium ThunderX, T88 pass 1.x - 2.1 */
|
|
MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
|
|
/* Cavium ThunderX, T81 pass 1.0 */
|
|
MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
|
|
{},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_30115
|
|
static const struct midr_range cavium_erratum_30115_cpus[] = {
|
|
/* Cavium ThunderX, T88 pass 1.x - 2.2 */
|
|
MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
|
|
/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
|
|
MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
|
|
/* Cavium ThunderX, T83 pass 1.0 */
|
|
MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
|
|
{},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
|
|
static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
|
|
{
|
|
ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
|
|
},
|
|
{
|
|
.midr_range.model = MIDR_QCOM_KRYO,
|
|
.matches = is_kryo_midr,
|
|
},
|
|
{},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
|
|
static const struct midr_range workaround_clean_cache[] = {
|
|
#if defined(CONFIG_ARM64_ERRATUM_826319) || \
|
|
defined(CONFIG_ARM64_ERRATUM_827319) || \
|
|
defined(CONFIG_ARM64_ERRATUM_824069)
|
|
/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
|
|
MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_819472
|
|
/* Cortex-A53 r0p[01] : ARM errata 819472 */
|
|
MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
|
|
#endif
|
|
{},
|
|
};
|
|
#endif
|
|
|
|
const struct arm64_cpu_capabilities arm64_errata[] = {
|
|
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
|
|
{
|
|
.desc = "ARM errata 826319, 827319, 824069, 819472",
|
|
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
|
|
ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
|
|
.cpu_enable = cpu_enable_cache_maint_trap,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_832075
|
|
{
|
|
/* Cortex-A57 r0p0 - r1p2 */
|
|
.desc = "ARM erratum 832075",
|
|
.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
|
|
0, 0,
|
|
1, 2),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_834220
|
|
{
|
|
/* Cortex-A57 r0p0 - r1p2 */
|
|
.desc = "ARM erratum 834220",
|
|
.capability = ARM64_WORKAROUND_834220,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
|
|
0, 0,
|
|
1, 2),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_843419
|
|
{
|
|
/* Cortex-A53 r0p[01234] */
|
|
.desc = "ARM erratum 843419",
|
|
.capability = ARM64_WORKAROUND_843419,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
|
|
MIDR_FIXED(0x4, BIT(8)),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_845719
|
|
{
|
|
/* Cortex-A53 r0p[01234] */
|
|
.desc = "ARM erratum 845719",
|
|
.capability = ARM64_WORKAROUND_845719,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_23154
|
|
{
|
|
/* Cavium ThunderX, pass 1.x */
|
|
.desc = "Cavium erratum 23154",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_23154,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_27456
|
|
{
|
|
.desc = "Cavium erratum 27456",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_27456,
|
|
ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_30115
|
|
{
|
|
.desc = "Cavium erratum 30115",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_30115,
|
|
ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
|
|
},
|
|
#endif
|
|
{
|
|
.desc = "Mismatched cache type (CTR_EL0)",
|
|
.capability = ARM64_MISMATCHED_CACHE_TYPE,
|
|
.matches = has_mismatched_cache_type,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.cpu_enable = cpu_enable_trap_ctr_access,
|
|
},
|
|
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
|
|
{
|
|
.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
|
|
.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
|
|
.matches = cpucap_multi_entry_cap_matches,
|
|
.match_list = qcom_erratum_1003_list,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
|
|
{
|
|
.desc = "Qualcomm erratum 1009, ARM erratum 1286807",
|
|
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
|
|
ERRATA_MIDR_RANGE_LIST(arm64_repeat_tlbi_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_858921
|
|
{
|
|
/* Cortex-A73 all versions */
|
|
.desc = "ARM erratum 858921",
|
|
.capability = ARM64_WORKAROUND_858921,
|
|
ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
|
|
{
|
|
.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
|
|
.cpu_enable = enable_smccc_arch_workaround_1,
|
|
ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_HARDEN_EL2_VECTORS
|
|
{
|
|
.desc = "EL2 vector hardening",
|
|
.capability = ARM64_HARDEN_EL2_VECTORS,
|
|
ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_SSBD
|
|
{
|
|
.desc = "Speculative Store Bypass Disable",
|
|
.capability = ARM64_SSBD,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_ssbd_mitigation,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1188873
|
|
{
|
|
/* Cortex-A76 r0p0 to r2p0 */
|
|
.desc = "ARM erratum 1188873",
|
|
.capability = ARM64_WORKAROUND_1188873,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1165522
|
|
{
|
|
/* Cortex-A76 r0p0 to r2p0 */
|
|
.desc = "ARM erratum 1165522",
|
|
.capability = ARM64_WORKAROUND_1165522,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
|
|
},
|
|
#endif
|
|
{
|
|
}
|
|
};
|