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40033a614e
Define the 32bit specific registers (SPSRs, cp15...). Most CPU registers are directly mapped to a 64bit register (r0->x0...). Only the SPSRs have separate registers. cp15 registers are also mapped into their 64bit counterpart in most cases. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
105 lines
4.6 KiB
C
105 lines
4.6 KiB
C
/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM_KVM_ASM_H__
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#define __ARM_KVM_ASM_H__
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/*
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* 0 is reserved as an invalid value.
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* Order *must* be kept in sync with the hyp switch code.
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*/
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#define MPIDR_EL1 1 /* MultiProcessor Affinity Register */
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#define CSSELR_EL1 2 /* Cache Size Selection Register */
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#define SCTLR_EL1 3 /* System Control Register */
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#define ACTLR_EL1 4 /* Auxilliary Control Register */
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#define CPACR_EL1 5 /* Coprocessor Access Control */
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#define TTBR0_EL1 6 /* Translation Table Base Register 0 */
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#define TTBR1_EL1 7 /* Translation Table Base Register 1 */
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#define TCR_EL1 8 /* Translation Control Register */
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#define ESR_EL1 9 /* Exception Syndrome Register */
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#define AFSR0_EL1 10 /* Auxilary Fault Status Register 0 */
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#define AFSR1_EL1 11 /* Auxilary Fault Status Register 1 */
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#define FAR_EL1 12 /* Fault Address Register */
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#define MAIR_EL1 13 /* Memory Attribute Indirection Register */
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#define VBAR_EL1 14 /* Vector Base Address Register */
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#define CONTEXTIDR_EL1 15 /* Context ID Register */
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#define TPIDR_EL0 16 /* Thread ID, User R/W */
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#define TPIDRRO_EL0 17 /* Thread ID, User R/O */
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#define TPIDR_EL1 18 /* Thread ID, Privileged */
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#define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */
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#define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */
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/* 32bit specific registers. Keep them at the end of the range */
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#define DACR32_EL2 21 /* Domain Access Control Register */
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#define IFSR32_EL2 22 /* Instruction Fault Status Register */
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#define FPEXC32_EL2 23 /* Floating-Point Exception Control Register */
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#define DBGVCR32_EL2 24 /* Debug Vector Catch Register */
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#define TEECR32_EL1 25 /* ThumbEE Configuration Register */
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#define TEEHBR32_EL1 26 /* ThumbEE Handler Base Register */
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#define NR_SYS_REGS 27
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/* 32bit mapping */
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#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
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#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
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#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
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#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
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#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
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#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
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#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
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#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
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#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
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#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
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#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
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#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
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#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
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#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
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#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
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#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
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#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
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#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
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#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
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#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
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#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
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#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
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#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
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#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
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#define c10_AMAIR (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
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#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
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#define NR_CP15_REGS (NR_SYS_REGS * 2)
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#define ARM_EXCEPTION_IRQ 0
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#define ARM_EXCEPTION_TRAP 1
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#ifndef __ASSEMBLY__
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struct kvm;
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struct kvm_vcpu;
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extern char __kvm_hyp_init[];
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extern char __kvm_hyp_init_end[];
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extern char __kvm_hyp_vector[];
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extern char __kvm_hyp_code_start[];
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extern char __kvm_hyp_code_end[];
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extern void __kvm_flush_vm_context(void);
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extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
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extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
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#endif
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#endif /* __ARM_KVM_ASM_H__ */
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