mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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974aa5630b
Common: - Python 3 support in kvm_stat - Accounting of slabs to kmemcg ARM: - Optimized arch timer handling for KVM/ARM - Improvements to the VGIC ITS code and introduction of an ITS reset ioctl - Unification of the 32-bit fault injection logic - More exact external abort matching logic PPC: - Support for running hashed page table (HPT) MMU mode on a host that is using the radix MMU mode; single threaded mode on POWER 9 is added as a pre-requisite - Resolution of merge conflicts with the last second 4.14 HPT fixes - Fixes and cleanups s390: - Some initial preparation patches for exitless interrupts and crypto - New capability for AIS migration - Fixes x86: - Improved emulation of LAPIC timer mode changes, MCi_STATUS MSRs, and after-reset state - Refined dependencies for VMX features - Fixes for nested SMI injection - A lot of cleanups -----BEGIN PGP SIGNATURE----- iQEcBAABCAAGBQJaDayXAAoJEED/6hsPKofo/3UH/3HvlcHt+ADTkCU1/iiKAs+i 0zngIOXIxgHDnV0ww6bV+Znww0BzTYgKCAXX76z603jdpDwG/pzQQcbLDF5ZoJnD sQtF10gZinWaRsHlfbLqjrHGL2pGDHO1UKBKLJ0bAIyORPZBxs7i+VmrY/blnr9c 0wsybJ8RbvwAxjsDL5jeX/z4NehPupmKUc4Lf0eZdSHwVOf9sjn+MP6jJ0r2JcIb D+zddPBiLStzN97t4gZpQsrlj3LKrDS+6hY+1TjSvlh+yHKFVFh58VhLm4DuDeb5 bYOAlWJ/gAWEzfvr5Ld+Nd7SqWWn/14logPkQ4gcU4BI/neAOzk4c6hJfCHl1nk= =593n -----END PGP SIGNATURE----- Merge tag 'kvm-4.15-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull KVM updates from Radim Krčmář: "First batch of KVM changes for 4.15 Common: - Python 3 support in kvm_stat - Accounting of slabs to kmemcg ARM: - Optimized arch timer handling for KVM/ARM - Improvements to the VGIC ITS code and introduction of an ITS reset ioctl - Unification of the 32-bit fault injection logic - More exact external abort matching logic PPC: - Support for running hashed page table (HPT) MMU mode on a host that is using the radix MMU mode; single threaded mode on POWER 9 is added as a pre-requisite - Resolution of merge conflicts with the last second 4.14 HPT fixes - Fixes and cleanups s390: - Some initial preparation patches for exitless interrupts and crypto - New capability for AIS migration - Fixes x86: - Improved emulation of LAPIC timer mode changes, MCi_STATUS MSRs, and after-reset state - Refined dependencies for VMX features - Fixes for nested SMI injection - A lot of cleanups" * tag 'kvm-4.15-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (89 commits) KVM: s390: provide a capability for AIS state migration KVM: s390: clear_io_irq() requests are not expected for adapter interrupts KVM: s390: abstract conversion between isc and enum irq_types KVM: s390: vsie: use common code functions for pinning KVM: s390: SIE considerations for AP Queue virtualization KVM: s390: document memory ordering for kvm_s390_vcpu_wakeup KVM: PPC: Book3S HV: Cosmetic post-merge cleanups KVM: arm/arm64: fix the incompatible matching for external abort KVM: arm/arm64: Unify 32bit fault injection KVM: arm/arm64: vgic-its: Implement KVM_DEV_ARM_ITS_CTRL_RESET KVM: arm/arm64: Document KVM_DEV_ARM_ITS_CTRL_RESET KVM: arm/arm64: vgic-its: Free caches when GITS_BASER Valid bit is cleared KVM: arm/arm64: vgic-its: New helper functions to free the caches KVM: arm/arm64: vgic-its: Remove kvm_its_unmap_device arm/arm64: KVM: Load the timer state when enabling the timer KVM: arm/arm64: Rework kvm_timer_should_fire KVM: arm/arm64: Get rid of kvm_timer_flush_hwstate KVM: arm/arm64: Avoid phys timer emulation in vcpu entry/exit KVM: arm/arm64: Move phys_timer_emulate function KVM: arm/arm64: Use kvm_arm_timer_set/get_reg for guest register traps ...
169 lines
4.1 KiB
C
169 lines
4.1 KiB
C
/*
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* arch/arm64/include/asm/arch_timer.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARCH_TIMER_H
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#define __ASM_ARCH_TIMER_H
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#include <asm/barrier.h>
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#include <asm/sysreg.h>
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#include <linux/bug.h>
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#include <linux/init.h>
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#include <linux/jump_label.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <clocksource/arm_arch_timer.h>
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#if IS_ENABLED(CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND)
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extern struct static_key_false arch_timer_read_ool_enabled;
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#define needs_unstable_timer_counter_workaround() \
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static_branch_unlikely(&arch_timer_read_ool_enabled)
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#else
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#define needs_unstable_timer_counter_workaround() false
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#endif
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enum arch_timer_erratum_match_type {
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ate_match_dt,
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ate_match_local_cap_id,
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ate_match_acpi_oem_info,
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};
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struct clock_event_device;
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struct arch_timer_erratum_workaround {
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enum arch_timer_erratum_match_type match_type;
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const void *id;
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const char *desc;
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u32 (*read_cntp_tval_el0)(void);
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u32 (*read_cntv_tval_el0)(void);
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u64 (*read_cntpct_el0)(void);
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u64 (*read_cntvct_el0)(void);
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int (*set_next_event_phys)(unsigned long, struct clock_event_device *);
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int (*set_next_event_virt)(unsigned long, struct clock_event_device *);
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};
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DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *,
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timer_unstable_counter_workaround);
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#define arch_timer_reg_read_stable(reg) \
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({ \
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u64 _val; \
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if (needs_unstable_timer_counter_workaround()) { \
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const struct arch_timer_erratum_workaround *wa; \
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preempt_disable_notrace(); \
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wa = __this_cpu_read(timer_unstable_counter_workaround); \
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if (wa && wa->read_##reg) \
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_val = wa->read_##reg(); \
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else \
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_val = read_sysreg(reg); \
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preempt_enable_notrace(); \
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} else { \
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_val = read_sysreg(reg); \
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} \
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_val; \
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})
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/*
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* These register accessors are marked inline so the compiler can
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* nicely work out which register we want, and chuck away the rest of
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* the code.
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*/
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static __always_inline
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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write_sysreg(val, cntp_ctl_el0);
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break;
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case ARCH_TIMER_REG_TVAL:
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write_sysreg(val, cntp_tval_el0);
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break;
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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write_sysreg(val, cntv_ctl_el0);
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break;
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case ARCH_TIMER_REG_TVAL:
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write_sysreg(val, cntv_tval_el0);
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break;
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}
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}
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isb();
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}
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static __always_inline
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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return read_sysreg(cntp_ctl_el0);
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case ARCH_TIMER_REG_TVAL:
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return arch_timer_reg_read_stable(cntp_tval_el0);
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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return read_sysreg(cntv_ctl_el0);
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case ARCH_TIMER_REG_TVAL:
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return arch_timer_reg_read_stable(cntv_tval_el0);
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}
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}
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BUG();
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}
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static inline u32 arch_timer_get_cntfrq(void)
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{
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return read_sysreg(cntfrq_el0);
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}
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static inline u32 arch_timer_get_cntkctl(void)
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{
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return read_sysreg(cntkctl_el1);
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}
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static inline void arch_timer_set_cntkctl(u32 cntkctl)
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{
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write_sysreg(cntkctl, cntkctl_el1);
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isb();
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}
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static inline u64 arch_counter_get_cntpct(void)
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{
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isb();
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return arch_timer_reg_read_stable(cntpct_el0);
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}
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static inline u64 arch_counter_get_cntvct(void)
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{
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isb();
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return arch_timer_reg_read_stable(cntvct_el0);
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}
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static inline int arch_timer_arch_init(void)
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{
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return 0;
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}
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#endif
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