mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 02:26:41 +07:00
d6b273bfdf
This patch de-asserts the reset line that is connected to the USB ULPI PHY on USB Host1. This patch should be included with the original USB host enablement set of patches of mx51 babbage hw, but was accidentily left out. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
266 lines
7.0 KiB
C
266 lines
7.0 KiB
C
/*
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* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/fsl_devices.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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#include <mach/imx-uart.h>
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#include <mach/iomux-mx51.h>
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#include <mach/mxc_ehci.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include "devices.h"
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#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
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#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
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#define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */
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/* USB_CTRL_1 */
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#define MX51_USB_CTRL_1_OFFSET 0x10
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#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
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#define MX51_USB_PLLDIV_12_MHZ 0x00
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#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
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#define MX51_USB_PLL_DIV_24_MHZ 0x02
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static struct platform_device *devices[] __initdata = {
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&mxc_fec_device,
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};
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static struct pad_desc mx51babbage_pads[] = {
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/* UART1 */
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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MX51_PAD_UART1_RTS__UART1_RTS,
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MX51_PAD_UART1_CTS__UART1_CTS,
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/* UART2 */
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MX51_PAD_UART2_RXD__UART2_RXD,
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MX51_PAD_UART2_TXD__UART2_TXD,
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/* UART3 */
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MX51_PAD_EIM_D25__UART3_RXD,
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MX51_PAD_EIM_D26__UART3_TXD,
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MX51_PAD_EIM_D27__UART3_RTS,
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MX51_PAD_EIM_D24__UART3_CTS,
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/* USB HOST1 */
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MX51_PAD_USBH1_CLK__USBH1_CLK,
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MX51_PAD_USBH1_DIR__USBH1_DIR,
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MX51_PAD_USBH1_NXT__USBH1_NXT,
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MX51_PAD_USBH1_DATA0__USBH1_DATA0,
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MX51_PAD_USBH1_DATA1__USBH1_DATA1,
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MX51_PAD_USBH1_DATA2__USBH1_DATA2,
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MX51_PAD_USBH1_DATA3__USBH1_DATA3,
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MX51_PAD_USBH1_DATA4__USBH1_DATA4,
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MX51_PAD_USBH1_DATA5__USBH1_DATA5,
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MX51_PAD_USBH1_DATA6__USBH1_DATA6,
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MX51_PAD_USBH1_DATA7__USBH1_DATA7,
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/* USB HUB reset line*/
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MX51_PAD_GPIO_1_7__GPIO1_7,
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};
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/* Serial ports */
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#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
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static struct imxuart_platform_data uart_pdata = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static inline void mxc_init_imx_uart(void)
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{
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mxc_register_device(&mxc_uart_device0, &uart_pdata);
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mxc_register_device(&mxc_uart_device1, &uart_pdata);
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mxc_register_device(&mxc_uart_device2, &uart_pdata);
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}
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#else /* !SERIAL_IMX */
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static inline void mxc_init_imx_uart(void)
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{
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}
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#endif /* SERIAL_IMX */
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static int gpio_usbh1_active(void)
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{
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struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
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struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
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int ret;
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/* Set USBH1_STP to GPIO and toggle it */
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mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
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ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
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if (ret) {
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pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
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return ret;
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}
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gpio_direction_output(BABBAGE_USBH1_STP, 0);
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gpio_set_value(BABBAGE_USBH1_STP, 1);
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msleep(100);
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gpio_free(BABBAGE_USBH1_STP);
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/* De-assert USB PHY RESETB */
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mxc_iomux_v3_setup_pad(&phyreset_gpio);
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ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
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if (ret) {
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pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
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return ret;
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}
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gpio_direction_output(BABBAGE_PHY_RESET, 1);
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return 0;
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}
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static inline void babbage_usbhub_reset(void)
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{
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int ret;
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/* Bring USB hub out of reset */
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ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
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if (ret) {
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printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
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return;
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}
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gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
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/* USB HUB RESET - De-assert USB HUB RESET_N */
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msleep(1);
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gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
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msleep(1);
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gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
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}
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/* This function is board specific as the bit mask for the plldiv will also
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be different for other Freescale SoCs, thus a common bitmask is not
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possible and cannot get place in /plat-mxc/ehci.c.*/
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static int initialize_otg_port(struct platform_device *pdev)
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{
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u32 v;
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void __iomem *usb_base;
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u32 usbother_base;
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usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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/* Set the PHY clock to 19.2MHz */
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
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v |= MX51_USB_PLL_DIV_19_2_MHZ;
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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iounmap(usb_base);
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return 0;
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}
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static int initialize_usbh1_port(struct platform_device *pdev)
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{
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u32 v;
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void __iomem *usb_base;
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u32 usbother_base;
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usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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/* The clock for the USBH1 ULPI port will come externally from the PHY. */
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v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
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__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
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iounmap(usb_base);
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return 0;
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}
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static struct mxc_usbh_platform_data dr_utmi_config = {
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.init = initialize_otg_port,
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.portsc = MXC_EHCI_UTMI_16BIT,
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.flags = MXC_EHCI_INTERNAL_PHY,
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};
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static struct fsl_usb2_platform_data usb_pdata = {
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.operating_mode = FSL_USB2_DR_DEVICE,
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.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
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};
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static struct mxc_usbh_platform_data usbh1_config = {
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.init = initialize_usbh1_port,
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.portsc = MXC_EHCI_MODE_ULPI,
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.flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
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};
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static int otg_mode_host;
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static int __init babbage_otg_mode(char *options)
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{
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if (!strcmp(options, "host"))
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otg_mode_host = 1;
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else if (!strcmp(options, "device"))
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otg_mode_host = 0;
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else
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pr_info("otg_mode neither \"host\" nor \"device\". "
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"Defaulting to device\n");
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return 0;
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}
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__setup("otg_mode=", babbage_otg_mode);
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/*
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* Board specific initialization.
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*/
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static void __init mxc_board_init(void)
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{
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struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
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mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
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ARRAY_SIZE(mx51babbage_pads));
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mxc_init_imx_uart();
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platform_add_devices(devices, ARRAY_SIZE(devices));
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if (otg_mode_host)
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mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
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else {
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initialize_otg_port(NULL);
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mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
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}
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gpio_usbh1_active();
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mxc_register_device(&mxc_usbh1_device, &usbh1_config);
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/* setback USBH1_STP to be function */
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mxc_iomux_v3_setup_pad(&usbh1stp);
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babbage_usbhub_reset();
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}
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static void __init mx51_babbage_timer_init(void)
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{
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mx51_clocks_init(32768, 24000000, 22579200, 0);
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}
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static struct sys_timer mxc_timer = {
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.init = mx51_babbage_timer_init,
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};
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MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
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/* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
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.phys_io = MX51_AIPS1_BASE_ADDR,
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.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
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.boot_params = PHYS_OFFSET + 0x100,
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.map_io = mx51_map_io,
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.init_irq = mx51_init_irq,
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.init_machine = mxc_board_init,
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.timer = &mxc_timer,
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MACHINE_END
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