mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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aa8d3e74f5
The Hip06 soc has same cpu topology compared with Hip05, four clusters and each cluster has quard Cortex-A57, but with different IO part, like HNS, SAS and PCI, they are all upgraded. There are also not same in ITS, MBIGEN and SMMU, etc. This patch adds the initial dts for hip06 d03 board. Note, there is no serial, because the soc use LPC uart, the serial node is not needed. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
308 lines
6.1 KiB
Plaintext
308 lines
6.1 KiB
Plaintext
/**
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* dts file for Hisilicon D03 Development Board
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*
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* Copyright (C) 2016 Hisilicon Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "hisilicon,hip06-d03";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cpu8>;
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};
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core1 {
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cpu = <&cpu9>;
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};
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core2 {
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cpu = <&cpu10>;
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};
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core3 {
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cpu = <&cpu11>;
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};
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};
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cluster3 {
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core0 {
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cpu = <&cpu12>;
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};
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core1 {
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cpu = <&cpu13>;
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};
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core2 {
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cpu = <&cpu14>;
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};
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core3 {
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cpu = <&cpu15>;
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};
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};
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};
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cpu0: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10000>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu1: cpu@10001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10001>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu2: cpu@10002 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10002>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu3: cpu@10003 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10003>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu4: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10100>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu5: cpu@10101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10101>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu6: cpu@10102 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10102>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu7: cpu@10103 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10103>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu8: cpu@10200 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10200>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu9: cpu@10201 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10201>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu10: cpu@10202 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10202>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu11: cpu@10203 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10203>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu12: cpu@10300 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10300>;
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enable-method = "psci";
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next-level-cache = <&cluster3_l2>;
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};
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cpu13: cpu@10301 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10301>;
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enable-method = "psci";
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next-level-cache = <&cluster3_l2>;
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};
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cpu14: cpu@10302 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10302>;
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enable-method = "psci";
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next-level-cache = <&cluster3_l2>;
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};
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cpu15: cpu@10303 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10303>;
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enable-method = "psci";
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next-level-cache = <&cluster3_l2>;
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};
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cluster0_l2: l2-cache0 {
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compatible = "cache";
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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};
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cluster2_l2: l2-cache2 {
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compatible = "cache";
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};
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cluster3_l2: l2-cache3 {
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compatible = "cache";
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};
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};
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gic: interrupt-controller@4d000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x30000>;
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reg = <0x0 0x4d000000 0 0x10000>, /* GICD */
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<0x0 0x4d100000 0 0x300000>, /* GICR */
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<0x0 0xfe000000 0 0x10000>, /* GICC */
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<0x0 0xfe010000 0 0x10000>, /* GICH */
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<0x0 0xfe020000 0 0x10000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its_dsa: interrupt-controller@c6000000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0xc6000000 0x0 0x40000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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pmu {
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compatible = "arm,cortex-a57-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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mbigen_pcie@a0080000 {
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compatible = "hisilicon,mbigen-v2";
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reg = <0x0 0xa0080000 0x0 0x10000>;
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mbigen_usb: intc_usb {
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msi-parent = <&its_dsa 0x40080>;
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interrupt-controller;
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#interrupt-cells = <2>;
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num-pins = <2>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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usb_ohci: ohci@a7030000 {
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compatible = "generic-ohci";
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reg = <0x0 0xa7030000 0x0 0x10000>;
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interrupt-parent = <&mbigen_usb>;
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interrupts = <64 4>;
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dma-coherent;
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status = "disabled";
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};
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usb_ehci: ehci@a7020000 {
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compatible = "generic-ehci";
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reg = <0x0 0xa7020000 0x0 0x10000>;
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interrupt-parent = <&mbigen_usb>;
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interrupts = <65 4>;
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dma-coherent;
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status = "disabled";
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};
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};
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};
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