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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8554926b3f
Add a new compatible string and additional clock ids for audio clock controller of the g12a SoC family. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190329160649.31603-2-jbrunet@baylibre.com
85 lines
2.7 KiB
C
85 lines
2.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (c) 2018 Baylibre SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
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#define __AXG_AUDIO_CLKC_BINDINGS_H
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#define AUD_CLKID_DDR_ARB 29
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#define AUD_CLKID_PDM 30
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#define AUD_CLKID_TDMIN_A 31
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#define AUD_CLKID_TDMIN_B 32
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#define AUD_CLKID_TDMIN_C 33
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#define AUD_CLKID_TDMIN_LB 34
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#define AUD_CLKID_TDMOUT_A 35
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#define AUD_CLKID_TDMOUT_B 36
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#define AUD_CLKID_TDMOUT_C 37
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#define AUD_CLKID_FRDDR_A 38
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#define AUD_CLKID_FRDDR_B 39
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#define AUD_CLKID_FRDDR_C 40
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#define AUD_CLKID_TODDR_A 41
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#define AUD_CLKID_TODDR_B 42
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#define AUD_CLKID_TODDR_C 43
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#define AUD_CLKID_LOOPBACK 44
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#define AUD_CLKID_SPDIFIN 45
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#define AUD_CLKID_SPDIFOUT 46
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#define AUD_CLKID_RESAMPLE 47
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#define AUD_CLKID_POWER_DETECT 48
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#define AUD_CLKID_MST_A_MCLK 49
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#define AUD_CLKID_MST_B_MCLK 50
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#define AUD_CLKID_MST_C_MCLK 51
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#define AUD_CLKID_MST_D_MCLK 52
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#define AUD_CLKID_MST_E_MCLK 53
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#define AUD_CLKID_MST_F_MCLK 54
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#define AUD_CLKID_SPDIFOUT_CLK 55
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#define AUD_CLKID_SPDIFIN_CLK 56
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#define AUD_CLKID_PDM_DCLK 57
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#define AUD_CLKID_PDM_SYSCLK 58
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#define AUD_CLKID_MST_A_SCLK 79
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#define AUD_CLKID_MST_B_SCLK 80
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#define AUD_CLKID_MST_C_SCLK 81
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#define AUD_CLKID_MST_D_SCLK 82
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#define AUD_CLKID_MST_E_SCLK 83
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#define AUD_CLKID_MST_F_SCLK 84
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#define AUD_CLKID_MST_A_LRCLK 86
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#define AUD_CLKID_MST_B_LRCLK 87
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#define AUD_CLKID_MST_C_LRCLK 88
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#define AUD_CLKID_MST_D_LRCLK 89
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#define AUD_CLKID_MST_E_LRCLK 90
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#define AUD_CLKID_MST_F_LRCLK 91
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#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
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#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
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#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
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#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
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#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
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#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
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#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
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#define AUD_CLKID_TDMIN_A_SCLK 123
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#define AUD_CLKID_TDMIN_B_SCLK 124
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#define AUD_CLKID_TDMIN_C_SCLK 125
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#define AUD_CLKID_TDMIN_LB_SCLK 126
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#define AUD_CLKID_TDMOUT_A_SCLK 127
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#define AUD_CLKID_TDMOUT_B_SCLK 128
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#define AUD_CLKID_TDMOUT_C_SCLK 129
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#define AUD_CLKID_TDMIN_A_LRCLK 130
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#define AUD_CLKID_TDMIN_B_LRCLK 131
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#define AUD_CLKID_TDMIN_C_LRCLK 132
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#define AUD_CLKID_TDMIN_LB_LRCLK 133
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#define AUD_CLKID_TDMOUT_A_LRCLK 134
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#define AUD_CLKID_TDMOUT_B_LRCLK 135
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#define AUD_CLKID_TDMOUT_C_LRCLK 136
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#define AUD_CLKID_SPDIFOUT_B 151
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#define AUD_CLKID_SPDIFOUT_B_CLK 152
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#define AUD_CLKID_TDM_MCLK_PAD0 155
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#define AUD_CLKID_TDM_MCLK_PAD1 156
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#define AUD_CLKID_TDM_LRCLK_PAD0 157
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#define AUD_CLKID_TDM_LRCLK_PAD1 158
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#define AUD_CLKID_TDM_LRCLK_PAD2 159
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#define AUD_CLKID_TDM_SCLK_PAD0 160
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#define AUD_CLKID_TDM_SCLK_PAD1 161
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#define AUD_CLKID_TDM_SCLK_PAD2 162
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#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
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