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98b0bf0273
If debug_regs.c is built with newer binutils, the resulting binary is "optimized"
by the assembler:
asm volatile("ss_start: "
"xor %%rax,%%rax\n\t"
"cpuid\n\t"
"movl $0x1a0,%%ecx\n\t"
"rdmsr\n\t"
: : : "rax", "ecx");
is translated to :
000000000040194e <ss_start>:
40194e: 31 c0 xor %eax,%eax <----- rax->eax?
401950: 0f a2 cpuid
401952: b9 a0 01 00 00 mov $0x1a0,%ecx
401957: 0f 32 rdmsr
As you can see rax is replaced with eax in target binary code.
This causes a difference is the length of xor instruction (2 Byte vs 3 Byte),
and makes the hard-coded instruction length check fail:
/* Instruction lengths starting at ss_start */
int ss_size[4] = {
3, /* xor */ <-------- 2 or 3?
2, /* cpuid */
5, /* mov */
2, /* rdmsr */
};
Encode the shorter version directly and, while at it, fix the "clobbers"
of the asm.
Cc: stable@vger.kernel.org
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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|---|---|---|
| .. | ||
| cr4_cpuid_sync_test.c | ||
| debug_regs.c | ||
| evmcs_test.c | ||
| hyperv_cpuid.c | ||
| mmio_warning_test.c | ||
| platform_info_test.c | ||
| set_sregs_test.c | ||
| smm_test.c | ||
| state_test.c | ||
| svm_vmcall_test.c | ||
| sync_regs_test.c | ||
| vmx_close_while_nested_test.c | ||
| vmx_dirty_log_test.c | ||
| vmx_preemption_timer_test.c | ||
| vmx_set_nested_state_test.c | ||
| vmx_tsc_adjust_test.c | ||
| xss_msr_test.c | ||