Palmer Dabbelt 4c3aeb82a0 RISC-V: Avoid using invalid intermediate translations ... This is almost entirely a comment. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>		2019-05-16 20:42:13 -07:00
..
vdso	riscv: vdso: drop unnecessary cc-ldoption	2019-04-29 16:35:10 -07:00
.gitignore	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00
asm-offsets.c	riscv: simplify the stack pointer setup in head.S	2019-04-25 14:51:10 -07:00
cacheinfo.c	RISC-V: Fix of_node_* refcount	2018-12-21 08:10:49 -08:00
cpu.c	RISC-V: Add RISC-V specific arch_match_cpu_phys_id	2019-04-30 09:47:44 -07:00
cpufeature.c	RISC-V: Assign hwcap as per comman capabilities.	2019-03-04 10:40:39 -08:00
entry.S	RISC-V: Access CSRs using CSR numbers	2019-05-16 20:42:11 -07:00
fpu.S	Extract FPU context operations from entry.S	2018-10-22 17:02:22 -07:00
ftrace.c	riscv: add missing newlines to printk messages	2019-02-11 15:34:56 -08:00
head.S	RISC-V: Avoid using invalid intermediate translations	2019-05-16 20:42:13 -07:00
irq.c	RISC-V: Add interrupt related SCAUSE defines in asm/csr.h	2019-05-16 20:42:11 -07:00
Makefile	RISC-V: Always compile mm/init.c with cmodel=medany and notrace	2019-03-26 18:25:06 -07:00
mcount-dyn.S	riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support	2018-04-02 19:59:13 -07:00
mcount.S	RISC-V: remove the unused return_to_handler export	2018-10-22 17:38:12 -07:00
module-sections.c	RISC-V: Support MODULE_SECTIONS mechanism on RV32	2019-01-07 08:19:20 -08:00
module.c	RISC-V: Use IS_ENABLED(CONFIG_CMODEL_MEDLOW)	2019-03-28 23:18:51 -07:00
module.lds	RISC-V: Add section of GOT.PLT for kernel module	2018-04-02 20:00:54 -07:00
perf_event.c	RISC-V: Access CSRs using CSR numbers	2019-05-16 20:42:11 -07:00
process.c	Auto-detect whether a FPU exists	2018-10-22 17:02:23 -07:00
ptrace.c	riscv: fix trace_sys_exit hook	2019-01-07 08:22:43 -08:00
reset.c	riscv: call pm_power_off from machine_halt / machine_power_off	2019-04-25 14:51:12 -07:00
riscv_ksyms.c	riscv: split the declaration of __copy_user	2018-06-09 12:34:31 -07:00
setup.c	riscv: cleanup the parse_dtb calling conventions	2019-04-25 14:51:11 -07:00
signal.c	riscv/signal: Fixup additional syscall restarting	2019-04-25 11:07:36 -07:00
smp.c	riscv: move flush_icache_{all,mm} to cacheflush.c	2019-05-16 20:42:12 -07:00
smpboot.c	RISC-V: Support nr_cpus command line option.	2019-05-16 20:42:04 -07:00
stacktrace.c	riscv: remove duplicate macros from ptrace.h	2019-04-25 14:51:11 -07:00
sys_riscv.c	RISC-V: Use a less ugly workaround for unused variable warnings	2018-08-28 12:58:36 -07:00
syscall_table.c	RISC-V: Make __NR_riscv_flush_icache visible to userspace	2018-01-07 15:14:37 -08:00
time.c	RISC-V: add of_node_put()	2018-12-21 08:11:08 -08:00
traps.c	riscv: Support BUG() in kernel module	2019-05-16 20:42:13 -07:00
vdso.c	riscv/vdso: don't clear PG_reserved	2019-03-05 21:07:18 -08:00
vmlinux.lds.S	Revert "RISC-V: Make BSS section as the last section in vmlinux.lds.S"	2019-02-11 15:24:45 -08:00