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de70d0e9d4
The i.MX 7ULP family of processors features NXP's advanced implementation of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics Processing Units (GPUs). This patch aims to add an initial support for imx7ulp. Note that we need configure power mode to Partial Stop mode 3 with system/bus clock enabled first as the default enabled STOP mode will gate off system/bus clock when execute WFI in MX7ULP SoC. And there's still no MXC_CPU_IMX7ULP IDs read from register as ULP has no anatop as before. So we encode one with 0xff in reverse order in case new ones will be in the future. Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
121 lines
2.7 KiB
C
121 lines
2.7 KiB
C
/*
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* Copyright 2004-2007, 2010-2015 Freescale Semiconductor, Inc.
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* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_MXC_H__
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#define __ASM_ARCH_MXC_H__
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#include <linux/types.h>
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#ifndef __ASM_ARCH_MXC_HARDWARE_H__
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#error "Do not include directly."
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#endif
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#define MXC_CPU_MX1 1
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#define MXC_CPU_MX21 21
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#define MXC_CPU_MX25 25
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#define MXC_CPU_MX27 27
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#define MXC_CPU_MX31 31
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#define MXC_CPU_MX35 35
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#define MXC_CPU_MX51 51
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#define MXC_CPU_MX53 53
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#define MXC_CPU_IMX6SL 0x60
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#define MXC_CPU_IMX6DL 0x61
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#define MXC_CPU_IMX6SX 0x62
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#define MXC_CPU_IMX6Q 0x63
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#define MXC_CPU_IMX6UL 0x64
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#define MXC_CPU_IMX6ULL 0x65
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/* virtual cpu id for i.mx6ulz */
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#define MXC_CPU_IMX6ULZ 0x6b
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#define MXC_CPU_IMX6SLL 0x67
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#define MXC_CPU_IMX7D 0x72
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#define MXC_CPU_IMX7ULP 0xff
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#define IMX_DDR_TYPE_LPDDR2 1
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#ifndef __ASSEMBLY__
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extern unsigned int __mxc_cpu_type;
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#ifdef CONFIG_SOC_IMX6SL
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static inline bool cpu_is_imx6sl(void)
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{
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return __mxc_cpu_type == MXC_CPU_IMX6SL;
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}
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#else
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static inline bool cpu_is_imx6sl(void)
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{
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return false;
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}
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#endif
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static inline bool cpu_is_imx6dl(void)
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{
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return __mxc_cpu_type == MXC_CPU_IMX6DL;
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}
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static inline bool cpu_is_imx6sx(void)
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{
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return __mxc_cpu_type == MXC_CPU_IMX6SX;
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}
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static inline bool cpu_is_imx6ul(void)
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{
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return __mxc_cpu_type == MXC_CPU_IMX6UL;
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}
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static inline bool cpu_is_imx6ull(void)
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{
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return __mxc_cpu_type == MXC_CPU_IMX6ULL;
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}
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static inline bool cpu_is_imx6ulz(void)
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{
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return __mxc_cpu_type == MXC_CPU_IMX6ULZ;
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}
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static inline bool cpu_is_imx6sll(void)
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{
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return __mxc_cpu_type == MXC_CPU_IMX6SLL;
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}
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static inline bool cpu_is_imx6q(void)
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{
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return __mxc_cpu_type == MXC_CPU_IMX6Q;
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}
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static inline bool cpu_is_imx7d(void)
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{
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return __mxc_cpu_type == MXC_CPU_IMX7D;
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}
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struct cpu_op {
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u32 cpu_rate;
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};
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int tzic_enable_wake(void);
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extern struct cpu_op *(*get_cpu_op)(int *op);
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#endif
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#define imx_readl readl_relaxed
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#define imx_readw readw_relaxed
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#define imx_writel writel_relaxed
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#define imx_writew writew_relaxed
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#endif /* __ASM_ARCH_MXC_H__ */
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