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The i.MX 7ULP family of processors features NXP's advanced implementation of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics Processing Units (GPUs). This patch aims to add an initial support for imx7ulp. Note that we need configure power mode to Partial Stop mode 3 with system/bus clock enabled first as the default enabled STOP mode will gate off system/bus clock when execute WFI in MX7ULP SoC. And there's still no MXC_CPU_IMX7ULP IDs read from register as ULP has no anatop as before. So we encode one with 0xff in reverse order in case new ones will be in the future. Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
32 lines
710 B
C
32 lines
710 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Author: Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <asm/mach/arch.h>
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#include "common.h"
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#include "hardware.h"
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static void __init imx7ulp_init_machine(void)
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{
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imx7ulp_pm_init();
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mxc_set_cpu_type(MXC_CPU_IMX7ULP);
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of_platform_default_populate(NULL, NULL, imx_soc_device_init());
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}
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static const char *const imx7ulp_dt_compat[] __initconst = {
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"fsl,imx7ulp",
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NULL,
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};
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DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
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.init_machine = imx7ulp_init_machine,
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.dt_compat = imx7ulp_dt_compat,
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MACHINE_END
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