mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 09:30:53 +07:00
4c18442e53
If timeout happens, kgd_hqd_destroy() just returns -ETIME leaving queue acquired. It may cause a deadlock, so the patch proposes to release queue before return. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
630 lines
16 KiB
C
630 lines
16 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/module.h>
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#include <linux/fdtable.h>
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#include <linux/uaccess.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "cikd.h"
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#include "cik_reg.h"
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#include "radeon_kfd.h"
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#include "radeon_ucode.h"
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#include <linux/firmware.h>
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#define CIK_PIPE_PER_MEC (4)
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struct kgd_mem {
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struct radeon_sa_bo *sa_bo;
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uint64_t gpu_addr;
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void *ptr;
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};
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static int init_sa_manager(struct kgd_dev *kgd, unsigned int size);
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static void fini_sa_manager(struct kgd_dev *kgd);
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static int allocate_mem(struct kgd_dev *kgd, size_t size, size_t alignment,
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enum kgd_memory_pool pool, struct kgd_mem **mem);
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static void free_mem(struct kgd_dev *kgd, struct kgd_mem *mem);
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static uint64_t get_vmem_size(struct kgd_dev *kgd);
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static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
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static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
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static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
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/*
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* Register access functions
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*/
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static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
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uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
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uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
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static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
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unsigned int vmid);
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static int kgd_init_memory(struct kgd_dev *kgd);
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static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t hpd_size, uint64_t hpd_gpu_addr);
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static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr);
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static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
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uint32_t pipe_id, uint32_t queue_id);
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static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
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unsigned int timeout, uint32_t pipe_id,
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uint32_t queue_id);
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static const struct kfd2kgd_calls kfd2kgd = {
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.init_sa_manager = init_sa_manager,
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.fini_sa_manager = fini_sa_manager,
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.allocate_mem = allocate_mem,
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.free_mem = free_mem,
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.get_vmem_size = get_vmem_size,
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.get_gpu_clock_counter = get_gpu_clock_counter,
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.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
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.program_sh_mem_settings = kgd_program_sh_mem_settings,
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.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
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.init_memory = kgd_init_memory,
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.init_pipeline = kgd_init_pipeline,
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.hqd_load = kgd_hqd_load,
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.hqd_is_occupied = kgd_hqd_is_occupied,
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.hqd_destroy = kgd_hqd_destroy,
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.get_fw_version = get_fw_version
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};
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static const struct kgd2kfd_calls *kgd2kfd;
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bool radeon_kfd_init(void)
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{
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#if defined(CONFIG_HSA_AMD_MODULE)
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bool (*kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls*,
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const struct kgd2kfd_calls**);
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kgd2kfd_init_p = symbol_request(kgd2kfd_init);
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if (kgd2kfd_init_p == NULL)
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return false;
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if (!kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
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symbol_put(kgd2kfd_init);
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kgd2kfd = NULL;
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return false;
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}
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return true;
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#elif defined(CONFIG_HSA_AMD)
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if (!kgd2kfd_init(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
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kgd2kfd = NULL;
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return false;
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}
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return true;
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#else
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return false;
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#endif
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}
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void radeon_kfd_fini(void)
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{
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if (kgd2kfd) {
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kgd2kfd->exit();
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symbol_put(kgd2kfd_init);
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}
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}
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void radeon_kfd_device_probe(struct radeon_device *rdev)
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{
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if (kgd2kfd)
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rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev, rdev->pdev);
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}
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void radeon_kfd_device_init(struct radeon_device *rdev)
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{
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if (rdev->kfd) {
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struct kgd2kfd_shared_resources gpu_resources = {
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.compute_vmid_bitmap = 0xFF00,
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.first_compute_pipe = 1,
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.compute_pipe_count = 8 - 1,
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};
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radeon_doorbell_get_kfd_info(rdev,
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&gpu_resources.doorbell_physical_address,
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&gpu_resources.doorbell_aperture_size,
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&gpu_resources.doorbell_start_offset);
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kgd2kfd->device_init(rdev->kfd, &gpu_resources);
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}
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}
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void radeon_kfd_device_fini(struct radeon_device *rdev)
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{
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if (rdev->kfd) {
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kgd2kfd->device_exit(rdev->kfd);
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rdev->kfd = NULL;
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}
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}
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void radeon_kfd_interrupt(struct radeon_device *rdev, const void *ih_ring_entry)
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{
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if (rdev->kfd)
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kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
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}
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void radeon_kfd_suspend(struct radeon_device *rdev)
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{
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if (rdev->kfd)
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kgd2kfd->suspend(rdev->kfd);
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}
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int radeon_kfd_resume(struct radeon_device *rdev)
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{
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int r = 0;
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if (rdev->kfd)
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r = kgd2kfd->resume(rdev->kfd);
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return r;
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}
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static u32 pool_to_domain(enum kgd_memory_pool p)
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{
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switch (p) {
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case KGD_POOL_FRAMEBUFFER: return RADEON_GEM_DOMAIN_VRAM;
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default: return RADEON_GEM_DOMAIN_GTT;
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}
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}
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static int init_sa_manager(struct kgd_dev *kgd, unsigned int size)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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int r;
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BUG_ON(kgd == NULL);
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r = radeon_sa_bo_manager_init(rdev, &rdev->kfd_bo,
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size,
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RADEON_GPU_PAGE_SIZE,
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RADEON_GEM_DOMAIN_GTT,
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RADEON_GEM_GTT_WC);
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if (r)
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return r;
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r = radeon_sa_bo_manager_start(rdev, &rdev->kfd_bo);
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if (r)
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radeon_sa_bo_manager_fini(rdev, &rdev->kfd_bo);
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return r;
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}
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static void fini_sa_manager(struct kgd_dev *kgd)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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BUG_ON(kgd == NULL);
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radeon_sa_bo_manager_suspend(rdev, &rdev->kfd_bo);
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radeon_sa_bo_manager_fini(rdev, &rdev->kfd_bo);
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}
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static int allocate_mem(struct kgd_dev *kgd, size_t size, size_t alignment,
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enum kgd_memory_pool pool, struct kgd_mem **mem)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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u32 domain;
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int r;
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BUG_ON(kgd == NULL);
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domain = pool_to_domain(pool);
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if (domain != RADEON_GEM_DOMAIN_GTT) {
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dev_err(rdev->dev,
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"Only allowed to allocate gart memory for kfd\n");
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return -EINVAL;
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}
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*mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
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if ((*mem) == NULL)
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return -ENOMEM;
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r = radeon_sa_bo_new(rdev, &rdev->kfd_bo, &(*mem)->sa_bo, size,
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alignment);
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if (r) {
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dev_err(rdev->dev, "failed to get memory for kfd (%d)\n", r);
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return r;
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}
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(*mem)->ptr = radeon_sa_bo_cpu_addr((*mem)->sa_bo);
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(*mem)->gpu_addr = radeon_sa_bo_gpu_addr((*mem)->sa_bo);
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return 0;
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}
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static void free_mem(struct kgd_dev *kgd, struct kgd_mem *mem)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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BUG_ON(kgd == NULL);
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radeon_sa_bo_free(rdev, &mem->sa_bo, NULL);
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kfree(mem);
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}
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static uint64_t get_vmem_size(struct kgd_dev *kgd)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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BUG_ON(kgd == NULL);
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return rdev->mc.real_vram_size;
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}
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static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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return rdev->asic->get_gpu_clock_counter(rdev);
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}
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static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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/* The sclk is in quantas of 10kHz */
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return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
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}
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static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
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{
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return (struct radeon_device *)kgd;
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}
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static void write_register(struct kgd_dev *kgd, uint32_t offset, uint32_t value)
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{
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struct radeon_device *rdev = get_radeon_device(kgd);
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writel(value, (void __iomem *)(rdev->rmmio + offset));
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}
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static uint32_t read_register(struct kgd_dev *kgd, uint32_t offset)
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{
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struct radeon_device *rdev = get_radeon_device(kgd);
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return readl((void __iomem *)(rdev->rmmio + offset));
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}
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static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
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uint32_t queue, uint32_t vmid)
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{
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struct radeon_device *rdev = get_radeon_device(kgd);
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uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
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mutex_lock(&rdev->srbm_mutex);
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write_register(kgd, SRBM_GFX_CNTL, value);
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}
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static void unlock_srbm(struct kgd_dev *kgd)
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{
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struct radeon_device *rdev = get_radeon_device(kgd);
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write_register(kgd, SRBM_GFX_CNTL, 0);
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mutex_unlock(&rdev->srbm_mutex);
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}
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static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t queue_id)
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{
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uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
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uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
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lock_srbm(kgd, mec, pipe, queue_id, 0);
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}
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static void release_queue(struct kgd_dev *kgd)
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{
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unlock_srbm(kgd);
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}
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static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
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uint32_t sh_mem_config,
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uint32_t sh_mem_ape1_base,
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uint32_t sh_mem_ape1_limit,
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uint32_t sh_mem_bases)
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{
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lock_srbm(kgd, 0, 0, 0, vmid);
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write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
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write_register(kgd, SH_MEM_APE1_BASE, sh_mem_ape1_base);
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write_register(kgd, SH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
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write_register(kgd, SH_MEM_BASES, sh_mem_bases);
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unlock_srbm(kgd);
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}
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static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
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unsigned int vmid)
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{
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/*
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* We have to assume that there is no outstanding mapping.
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* The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0
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* because a mapping is in progress or because a mapping finished and
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* the SW cleared it.
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* So the protocol is to always wait & clear.
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*/
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uint32_t pasid_mapping = (pasid == 0) ? 0 :
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(uint32_t)pasid | ATC_VMID_PASID_MAPPING_VALID;
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write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t),
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pasid_mapping);
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while (!(read_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) &
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(1U << vmid)))
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cpu_relax();
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write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
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return 0;
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}
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static int kgd_init_memory(struct kgd_dev *kgd)
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{
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/*
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* Configure apertures:
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* LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
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* Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
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* GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
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*/
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int i;
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uint32_t sh_mem_bases = PRIVATE_BASE(0x6000) | SHARED_BASE(0x6000);
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for (i = 8; i < 16; i++) {
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uint32_t sh_mem_config;
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lock_srbm(kgd, 0, 0, 0, i);
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sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
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sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
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write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
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write_register(kgd, SH_MEM_BASES, sh_mem_bases);
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/* Scratch aperture is not supported for now. */
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write_register(kgd, SH_STATIC_MEM_CONFIG, 0);
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/* APE1 disabled for now. */
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write_register(kgd, SH_MEM_APE1_BASE, 1);
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write_register(kgd, SH_MEM_APE1_LIMIT, 0);
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unlock_srbm(kgd);
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}
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return 0;
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}
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static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t hpd_size, uint64_t hpd_gpu_addr)
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{
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uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
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uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
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lock_srbm(kgd, mec, pipe, 0, 0);
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write_register(kgd, CP_HPD_EOP_BASE_ADDR,
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lower_32_bits(hpd_gpu_addr >> 8));
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write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI,
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upper_32_bits(hpd_gpu_addr >> 8));
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write_register(kgd, CP_HPD_EOP_VMID, 0);
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write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size);
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unlock_srbm(kgd);
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return 0;
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}
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static inline struct cik_mqd *get_mqd(void *mqd)
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{
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return (struct cik_mqd *)mqd;
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}
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static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr)
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{
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uint32_t wptr_shadow, is_wptr_shadow_valid;
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struct cik_mqd *m;
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m = get_mqd(mqd);
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is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
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acquire_queue(kgd, pipe_id, queue_id);
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write_register(kgd, CP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
|
|
write_register(kgd, CP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
|
|
write_register(kgd, CP_MQD_CONTROL, m->cp_mqd_control);
|
|
|
|
write_register(kgd, CP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
|
|
write_register(kgd, CP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
|
|
write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
|
|
|
|
write_register(kgd, CP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
|
|
write_register(kgd, CP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
|
|
write_register(kgd, CP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
|
|
|
|
write_register(kgd, CP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
|
|
|
|
write_register(kgd, CP_HQD_PERSISTENT_STATE,
|
|
m->cp_hqd_persistent_state);
|
|
write_register(kgd, CP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
|
|
write_register(kgd, CP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
|
|
|
|
write_register(kgd, CP_HQD_ATOMIC0_PREOP_LO,
|
|
m->cp_hqd_atomic0_preop_lo);
|
|
|
|
write_register(kgd, CP_HQD_ATOMIC0_PREOP_HI,
|
|
m->cp_hqd_atomic0_preop_hi);
|
|
|
|
write_register(kgd, CP_HQD_ATOMIC1_PREOP_LO,
|
|
m->cp_hqd_atomic1_preop_lo);
|
|
|
|
write_register(kgd, CP_HQD_ATOMIC1_PREOP_HI,
|
|
m->cp_hqd_atomic1_preop_hi);
|
|
|
|
write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR,
|
|
m->cp_hqd_pq_rptr_report_addr_lo);
|
|
|
|
write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
|
|
m->cp_hqd_pq_rptr_report_addr_hi);
|
|
|
|
write_register(kgd, CP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
|
|
|
|
write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR,
|
|
m->cp_hqd_pq_wptr_poll_addr_lo);
|
|
|
|
write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR_HI,
|
|
m->cp_hqd_pq_wptr_poll_addr_hi);
|
|
|
|
write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL,
|
|
m->cp_hqd_pq_doorbell_control);
|
|
|
|
write_register(kgd, CP_HQD_VMID, m->cp_hqd_vmid);
|
|
|
|
write_register(kgd, CP_HQD_QUANTUM, m->cp_hqd_quantum);
|
|
|
|
write_register(kgd, CP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
|
|
write_register(kgd, CP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
|
|
|
|
write_register(kgd, CP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
|
|
|
|
if (is_wptr_shadow_valid)
|
|
write_register(kgd, CP_HQD_PQ_WPTR, wptr_shadow);
|
|
|
|
write_register(kgd, CP_HQD_ACTIVE, m->cp_hqd_active);
|
|
release_queue(kgd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
|
|
uint32_t pipe_id, uint32_t queue_id)
|
|
{
|
|
uint32_t act;
|
|
bool retval = false;
|
|
uint32_t low, high;
|
|
|
|
acquire_queue(kgd, pipe_id, queue_id);
|
|
act = read_register(kgd, CP_HQD_ACTIVE);
|
|
if (act) {
|
|
low = lower_32_bits(queue_address >> 8);
|
|
high = upper_32_bits(queue_address >> 8);
|
|
|
|
if (low == read_register(kgd, CP_HQD_PQ_BASE) &&
|
|
high == read_register(kgd, CP_HQD_PQ_BASE_HI))
|
|
retval = true;
|
|
}
|
|
release_queue(kgd);
|
|
return retval;
|
|
}
|
|
|
|
static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
|
|
unsigned int timeout, uint32_t pipe_id,
|
|
uint32_t queue_id)
|
|
{
|
|
uint32_t temp;
|
|
|
|
acquire_queue(kgd, pipe_id, queue_id);
|
|
write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL, 0);
|
|
|
|
write_register(kgd, CP_HQD_DEQUEUE_REQUEST, reset_type);
|
|
|
|
while (true) {
|
|
temp = read_register(kgd, CP_HQD_ACTIVE);
|
|
if (temp & 0x1)
|
|
break;
|
|
if (timeout == 0) {
|
|
pr_err("kfd: cp queue preemption time out (%dms)\n",
|
|
temp);
|
|
release_queue(kgd);
|
|
return -ETIME;
|
|
}
|
|
msleep(20);
|
|
timeout -= 20;
|
|
}
|
|
|
|
release_queue(kgd);
|
|
return 0;
|
|
}
|
|
|
|
static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
|
|
{
|
|
struct radeon_device *rdev = (struct radeon_device *) kgd;
|
|
const union radeon_firmware_header *hdr;
|
|
|
|
BUG_ON(kgd == NULL || rdev->mec_fw == NULL);
|
|
|
|
switch (type) {
|
|
case KGD_ENGINE_PFP:
|
|
hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_ME:
|
|
hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_CE:
|
|
hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_MEC1:
|
|
hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_MEC2:
|
|
hdr = (const union radeon_firmware_header *)
|
|
rdev->mec2_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_RLC:
|
|
hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_SDMA:
|
|
hdr = (const union radeon_firmware_header *)
|
|
rdev->sdma_fw->data;
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
if (hdr == NULL)
|
|
return 0;
|
|
|
|
/* Only 12 bit in use*/
|
|
return hdr->common.ucode_version;
|
|
}
|