mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 05:46:39 +07:00
3836309d93
CONFIG_HOTPLUG is going away as an option so __devinit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
532 lines
14 KiB
C
532 lines
14 KiB
C
/*
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* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* Based on code from Freescale,
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* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/basic_mmio_gpio.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/module.h>
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#include <asm-generic/bug.h>
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#include <asm/mach/irq.h>
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enum mxc_gpio_hwtype {
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IMX1_GPIO, /* runs on i.mx1 */
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IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
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IMX31_GPIO, /* runs on i.mx31 */
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IMX35_GPIO, /* runs on all other i.mx */
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};
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/* device type dependent stuff */
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struct mxc_gpio_hwdata {
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unsigned dr_reg;
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unsigned gdir_reg;
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unsigned psr_reg;
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unsigned icr1_reg;
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unsigned icr2_reg;
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unsigned imr_reg;
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unsigned isr_reg;
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int edge_sel_reg;
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unsigned low_level;
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unsigned high_level;
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unsigned rise_edge;
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unsigned fall_edge;
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};
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struct mxc_gpio_port {
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struct list_head node;
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void __iomem *base;
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int irq;
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int irq_high;
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struct irq_domain *domain;
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struct bgpio_chip bgc;
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u32 both_edges;
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};
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static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
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.dr_reg = 0x1c,
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.gdir_reg = 0x00,
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.psr_reg = 0x24,
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.icr1_reg = 0x28,
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.icr2_reg = 0x2c,
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.imr_reg = 0x30,
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.isr_reg = 0x34,
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.edge_sel_reg = -EINVAL,
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.low_level = 0x03,
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.high_level = 0x02,
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.rise_edge = 0x00,
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.fall_edge = 0x01,
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};
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static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
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.dr_reg = 0x00,
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.gdir_reg = 0x04,
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.psr_reg = 0x08,
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.icr1_reg = 0x0c,
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.icr2_reg = 0x10,
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.imr_reg = 0x14,
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.isr_reg = 0x18,
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.edge_sel_reg = -EINVAL,
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.low_level = 0x00,
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.high_level = 0x01,
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.rise_edge = 0x02,
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.fall_edge = 0x03,
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};
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static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
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.dr_reg = 0x00,
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.gdir_reg = 0x04,
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.psr_reg = 0x08,
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.icr1_reg = 0x0c,
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.icr2_reg = 0x10,
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.imr_reg = 0x14,
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.isr_reg = 0x18,
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.edge_sel_reg = 0x1c,
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.low_level = 0x00,
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.high_level = 0x01,
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.rise_edge = 0x02,
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.fall_edge = 0x03,
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};
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static enum mxc_gpio_hwtype mxc_gpio_hwtype;
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static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
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#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
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#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
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#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
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#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
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#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
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#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
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#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
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#define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
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#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
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#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
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#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
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#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
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#define GPIO_INT_BOTH_EDGES 0x4
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static struct platform_device_id mxc_gpio_devtype[] = {
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{
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.name = "imx1-gpio",
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.driver_data = IMX1_GPIO,
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}, {
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.name = "imx21-gpio",
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.driver_data = IMX21_GPIO,
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}, {
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.name = "imx31-gpio",
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.driver_data = IMX31_GPIO,
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}, {
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.name = "imx35-gpio",
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.driver_data = IMX35_GPIO,
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}, {
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/* sentinel */
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}
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};
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static const struct of_device_id mxc_gpio_dt_ids[] = {
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{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
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{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
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{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
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{ .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
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{ /* sentinel */ }
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};
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/*
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* MX2 has one interrupt *for all* gpio ports. The list is used
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* to save the references to all ports, so that mx2_gpio_irq_handler
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* can walk through all interrupt status registers.
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*/
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static LIST_HEAD(mxc_gpio_ports);
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/* Note: This driver assumes 32 GPIOs are handled in one register */
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static int gpio_set_irq_type(struct irq_data *d, u32 type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mxc_gpio_port *port = gc->private;
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u32 bit, val;
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u32 gpio_idx = d->hwirq;
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u32 gpio = port->bgc.gc.base + gpio_idx;
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int edge;
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void __iomem *reg = port->base;
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port->both_edges &= ~(1 << gpio_idx);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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edge = GPIO_INT_RISE_EDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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edge = GPIO_INT_FALL_EDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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if (GPIO_EDGE_SEL >= 0) {
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edge = GPIO_INT_BOTH_EDGES;
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} else {
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val = gpio_get_value(gpio);
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if (val) {
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edge = GPIO_INT_LOW_LEV;
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pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
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} else {
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edge = GPIO_INT_HIGH_LEV;
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pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
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}
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port->both_edges |= 1 << gpio_idx;
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}
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break;
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case IRQ_TYPE_LEVEL_LOW:
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edge = GPIO_INT_LOW_LEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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edge = GPIO_INT_HIGH_LEV;
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break;
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default:
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return -EINVAL;
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}
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if (GPIO_EDGE_SEL >= 0) {
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val = readl(port->base + GPIO_EDGE_SEL);
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if (edge == GPIO_INT_BOTH_EDGES)
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writel(val | (1 << gpio_idx),
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port->base + GPIO_EDGE_SEL);
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else
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writel(val & ~(1 << gpio_idx),
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port->base + GPIO_EDGE_SEL);
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}
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if (edge != GPIO_INT_BOTH_EDGES) {
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reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
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bit = gpio_idx & 0xf;
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val = readl(reg) & ~(0x3 << (bit << 1));
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writel(val | (edge << (bit << 1)), reg);
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}
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writel(1 << gpio_idx, port->base + GPIO_ISR);
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return 0;
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}
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static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
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{
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void __iomem *reg = port->base;
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u32 bit, val;
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int edge;
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reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
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bit = gpio & 0xf;
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val = readl(reg);
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edge = (val >> (bit << 1)) & 3;
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val &= ~(0x3 << (bit << 1));
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if (edge == GPIO_INT_HIGH_LEV) {
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edge = GPIO_INT_LOW_LEV;
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pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
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} else if (edge == GPIO_INT_LOW_LEV) {
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edge = GPIO_INT_HIGH_LEV;
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pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
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} else {
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pr_err("mxc: invalid configuration for GPIO %d: %x\n",
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gpio, edge);
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return;
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}
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writel(val | (edge << (bit << 1)), reg);
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}
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/* handle 32 interrupts in one status register */
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static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
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{
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while (irq_stat != 0) {
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int irqoffset = fls(irq_stat) - 1;
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if (port->both_edges & (1 << irqoffset))
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mxc_flip_edge(port, irqoffset);
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generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
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irq_stat &= ~(1 << irqoffset);
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}
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}
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/* MX1 and MX3 has one interrupt *per* gpio port */
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static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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u32 irq_stat;
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struct mxc_gpio_port *port = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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chained_irq_enter(chip, desc);
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irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
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mxc_gpio_irq_handler(port, irq_stat);
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chained_irq_exit(chip, desc);
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}
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/* MX2 has one interrupt *for all* gpio ports */
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static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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u32 irq_msk, irq_stat;
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struct mxc_gpio_port *port;
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/* walk through all interrupt status registers */
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list_for_each_entry(port, &mxc_gpio_ports, node) {
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irq_msk = readl(port->base + GPIO_IMR);
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if (!irq_msk)
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continue;
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irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
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if (irq_stat)
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mxc_gpio_irq_handler(port, irq_stat);
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}
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}
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/*
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* Set interrupt number "irq" in the GPIO as a wake-up source.
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* While system is running, all registered GPIO interrupts need to have
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* wake-up enabled. When system is suspended, only selected GPIO interrupts
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* need to have wake-up enabled.
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* @param irq interrupt source number
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* @param enable enable as wake-up if equal to non-zero
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* @return This function returns 0 on success.
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*/
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static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mxc_gpio_port *port = gc->private;
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u32 gpio_idx = d->hwirq;
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if (enable) {
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if (port->irq_high && (gpio_idx >= 16))
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enable_irq_wake(port->irq_high);
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else
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enable_irq_wake(port->irq);
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} else {
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if (port->irq_high && (gpio_idx >= 16))
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disable_irq_wake(port->irq_high);
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else
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disable_irq_wake(port->irq);
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}
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return 0;
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}
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static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
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port->base, handle_level_irq);
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gc->private = port;
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = gpio_set_irq_type;
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ct->chip.irq_set_wake = gpio_set_wake_irq;
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ct->regs.ack = GPIO_ISR;
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ct->regs.mask = GPIO_IMR;
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irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
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IRQ_NOREQUEST, 0);
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}
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static void mxc_gpio_get_hw(struct platform_device *pdev)
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{
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const struct of_device_id *of_id =
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of_match_device(mxc_gpio_dt_ids, &pdev->dev);
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enum mxc_gpio_hwtype hwtype;
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if (of_id)
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pdev->id_entry = of_id->data;
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hwtype = pdev->id_entry->driver_data;
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if (mxc_gpio_hwtype) {
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/*
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* The driver works with a reasonable presupposition,
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* that is all gpio ports must be the same type when
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* running on one soc.
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*/
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BUG_ON(mxc_gpio_hwtype != hwtype);
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return;
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}
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if (hwtype == IMX35_GPIO)
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mxc_gpio_hwdata = &imx35_gpio_hwdata;
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else if (hwtype == IMX31_GPIO)
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mxc_gpio_hwdata = &imx31_gpio_hwdata;
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else
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mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
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mxc_gpio_hwtype = hwtype;
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}
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static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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struct mxc_gpio_port *port =
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container_of(bgc, struct mxc_gpio_port, bgc);
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return irq_find_mapping(port->domain, offset);
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}
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static int mxc_gpio_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct mxc_gpio_port *port;
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struct resource *iores;
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int irq_base;
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int err;
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mxc_gpio_get_hw(pdev);
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port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
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if (!port)
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return -ENOMEM;
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iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!iores) {
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err = -ENODEV;
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goto out_kfree;
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}
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if (!request_mem_region(iores->start, resource_size(iores),
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pdev->name)) {
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err = -EBUSY;
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goto out_kfree;
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}
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port->base = ioremap(iores->start, resource_size(iores));
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if (!port->base) {
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err = -ENOMEM;
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goto out_release_mem;
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}
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port->irq_high = platform_get_irq(pdev, 1);
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port->irq = platform_get_irq(pdev, 0);
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if (port->irq < 0) {
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err = -EINVAL;
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goto out_iounmap;
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}
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/* disable the interrupt and clear the status */
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writel(0, port->base + GPIO_IMR);
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writel(~0, port->base + GPIO_ISR);
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if (mxc_gpio_hwtype == IMX21_GPIO) {
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/*
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* Setup one handler for all GPIO interrupts. Actually setting
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* the handler is needed only once, but doing it for every port
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* is more robust and easier.
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*/
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irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
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} else {
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/* setup one handler for each entry */
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irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
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irq_set_handler_data(port->irq, port);
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if (port->irq_high > 0) {
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/* setup handler for GPIO 16 to 31 */
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irq_set_chained_handler(port->irq_high,
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mx3_gpio_irq_handler);
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irq_set_handler_data(port->irq_high, port);
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}
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}
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err = bgpio_init(&port->bgc, &pdev->dev, 4,
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port->base + GPIO_PSR,
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port->base + GPIO_DR, NULL,
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port->base + GPIO_GDIR, NULL, 0);
|
|
if (err)
|
|
goto out_iounmap;
|
|
|
|
port->bgc.gc.to_irq = mxc_gpio_to_irq;
|
|
port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
|
|
pdev->id * 32;
|
|
|
|
err = gpiochip_add(&port->bgc.gc);
|
|
if (err)
|
|
goto out_bgpio_remove;
|
|
|
|
irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
|
|
if (irq_base < 0) {
|
|
err = irq_base;
|
|
goto out_gpiochip_remove;
|
|
}
|
|
|
|
port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
|
|
&irq_domain_simple_ops, NULL);
|
|
if (!port->domain) {
|
|
err = -ENODEV;
|
|
goto out_irqdesc_free;
|
|
}
|
|
|
|
/* gpio-mxc can be a generic irq chip */
|
|
mxc_gpio_init_gc(port, irq_base);
|
|
|
|
list_add_tail(&port->node, &mxc_gpio_ports);
|
|
|
|
return 0;
|
|
|
|
out_irqdesc_free:
|
|
irq_free_descs(irq_base, 32);
|
|
out_gpiochip_remove:
|
|
WARN_ON(gpiochip_remove(&port->bgc.gc) < 0);
|
|
out_bgpio_remove:
|
|
bgpio_remove(&port->bgc);
|
|
out_iounmap:
|
|
iounmap(port->base);
|
|
out_release_mem:
|
|
release_mem_region(iores->start, resource_size(iores));
|
|
out_kfree:
|
|
kfree(port);
|
|
dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
|
|
return err;
|
|
}
|
|
|
|
static struct platform_driver mxc_gpio_driver = {
|
|
.driver = {
|
|
.name = "gpio-mxc",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = mxc_gpio_dt_ids,
|
|
},
|
|
.probe = mxc_gpio_probe,
|
|
.id_table = mxc_gpio_devtype,
|
|
};
|
|
|
|
static int __init gpio_mxc_init(void)
|
|
{
|
|
return platform_driver_register(&mxc_gpio_driver);
|
|
}
|
|
postcore_initcall(gpio_mxc_init);
|
|
|
|
MODULE_AUTHOR("Freescale Semiconductor, "
|
|
"Daniel Mack <danielncaiaq.de>, "
|
|
"Juergen Beisert <kernel@pengutronix.de>");
|
|
MODULE_DESCRIPTION("Freescale MXC GPIO");
|
|
MODULE_LICENSE("GPL");
|