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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c1bfa985de
All of the keystone devices have a separate register to hold post divider value for main pll clock. Currently the fixed-postdiv value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to use a value of 2 for this. Now that we have fixed this in the pll clock driver change the dt bindings for the same. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
78 lines
1.9 KiB
Plaintext
78 lines
1.9 KiB
Plaintext
/*
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* Copyright 2014 Texas Instruments, Inc.
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*
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* Keystone 2 Edison SoC specific device tree
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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clocks {
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mainpllclk: mainpllclk@2310110 {
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#clock-cells = <0>;
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compatible = "ti,keystone,main-pll-clock";
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clocks = <&refclksys>;
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reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
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reg-names = "control", "multiplier", "post-divider";
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};
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papllclk: papllclk@2620358 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkpass>;
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clock-output-names = "papllclk";
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reg = <0x02620358 4>;
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reg-names = "control";
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};
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ddr3apllclk: ddr3apllclk@2620360 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkddr3a>;
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clock-output-names = "ddr-3a-pll-clk";
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reg = <0x02620360 4>;
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reg-names = "control";
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};
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clkusb1: clkusb1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk16>;
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clock-output-names = "usb1";
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reg = <0x02350004 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <0>;
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};
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clkhyperlink0: clkhyperlink0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "hyperlink-0";
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reg = <0x02350030 0xb00>, <0x02350014 0x400>;
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reg-names = "control", "domain";
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domain-id = <5>;
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};
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clkpcie1: clkpcie1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "pcie1";
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reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
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reg-names = "control", "domain";
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domain-id = <18>;
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};
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clkxge: clkxge {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "xge";
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reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
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reg-names = "control", "domain";
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domain-id = <29>;
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};
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};
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