mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 14:30:55 +07:00
f5dcb68086
Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses Conflicts: arch/arm64/boot/dts/arm/juno-motherboard.dtsi Trivial add/add conflict with our dt branch. Resolution: take both sides. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVi4RRAAoJEFk3GJrT+8ZljIcQAIsqxM/o0drd90xTJ6ex9h0B RmqVLTDgesHmBacJ+SBsa9/ybFIM1uErByftc1dmKankEQVXW3wcH7keQnoStPT2 zTEjadHgZ/ARYjV/oG5oohjfDZpO1kECVHL8O8RmcWxgzRB3az1IW2eD+dzrga/Y R7K6D8rDHMADIUmv0e0DzvQEbSUYdCx3rBND1qZznwZDP3NoivLkOG5MTraccLbQ ouCRoZtyNYD5Lxk+BHLBepnxAa0Ggc6IjEmiUv8fF2OYdu0OruMliT4rcAtOSmzg 2Y7pP85h8u0CxbJDkOyc+2BELyKo7Hv97XtDNNbRYABTMXdskRIadXt4Sh4mwFtM nvlhB4ovbIX7noECJToEkSAgmStLSUwA3R6+DVdLbeQY4uSuXuTRhiWHMyQB6va9 CdjJDk2RE0dZ77c5ZoUnUDtBe4cULU/n4agpYkKMf/HcpnqMUwZzP4KZbbPMBpgL 0CVTt3YrEcjoU7g0SFHhOGPSgl4yIXKU2eHEscokyFYLrS5zRWepmUEmlSoaWn+W p7pJE65TvOGf2xbaWI+UBeK/3ZG7XAP8qUfhsi7NS4bV6oFCk/foqsWAuru0H7OW 2Gk8fuF0qLgE1eFWQp8BHZ4IUeytoWbnGhhHXh8zH39SKAVncOiAGDNfuEP9CyXJ fZFfruYrnz2emOwj2v9m =02Gm -----END PGP SIGNATURE----- Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Kevin Hilman: "Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) drivers: soc: sunxi: Introduce SoC driver to map SRAMs arm-cci: Add aliases for PMU events arm-cci: Add CCI-500 PMU support arm-cci: Sanitise CCI400 PMU driver specific code arm-cci: Abstract handling for CCI events arm-cci: Abstract out the PMU counter details arm-cci: Cleanup PMU driver code arm-cci: Do not enable CCI-400 PMU by default firmware: qcom: scm: Add HDCP Support ARM: berlin: add an ADC node for the BG2Q ARM: berlin: remove useless chip and system ctrl compatibles clk: berlin: drop direct of_iomap of nodes reg property ARM: berlin: move BG2Q clock node ARM: berlin: move BG2CD clock node ARM: berlin: move BG2 clock node clk: berlin: prepare simple-mfd conversion pinctrl: berlin: drop SoC stub provided regmap ARM: berlin: move pinctrl to simple-mfd nodes pinctrl: berlin: prepare to use regmap provided by syscon reset: berlin: drop arch_initcall initialization ...
451 lines
11 KiB
Plaintext
451 lines
11 KiB
Plaintext
/*
|
|
* Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
|
|
*
|
|
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
|
*
|
|
* based on GPL'ed 2.6 kernel sources
|
|
* (c) Marvell International Ltd.
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*
|
|
* Or, alternatively,
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
#include <dt-bindings/clock/berlin2.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/ {
|
|
model = "Marvell Armada 1500-mini (BG2CD) SoC";
|
|
compatible = "marvell,berlin2cd", "marvell,berlin";
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a9";
|
|
device_type = "cpu";
|
|
next-level-cache = <&l2>;
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
refclk: oscillator {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <25000000>;
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
|
|
ranges = <0 0xf7000000 0x1000000>;
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sdhci0: sdhci@ab0000 {
|
|
compatible = "mrvl,pxav3-mmc";
|
|
reg = <0xab0000 0x200>;
|
|
clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
|
|
clock-names = "io", "core";
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
l2: l2-cache-controller@ac0000 {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0xac0000 0x1000>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
};
|
|
|
|
gic: interrupt-controller@ad1000 {
|
|
compatible = "arm,cortex-a9-gic";
|
|
reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
local-timer@ad0600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0xad0600 0x20>;
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
clocks = <&chip_clk CLKID_TWD>;
|
|
};
|
|
|
|
usb_phy0: usb-phy@b74000 {
|
|
compatible = "marvell,berlin2cd-usb-phy";
|
|
reg = <0xb74000 0x128>;
|
|
#phy-cells = <0>;
|
|
resets = <&chip_rst 0x178 23>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_phy1: usb-phy@b78000 {
|
|
compatible = "marvell,berlin2cd-usb-phy";
|
|
reg = <0xb78000 0x128>;
|
|
#phy-cells = <0>;
|
|
resets = <&chip_rst 0x178 24>;
|
|
status = "disabled";
|
|
};
|
|
|
|
eth1: ethernet@b90000 {
|
|
compatible = "marvell,pxa168-eth";
|
|
reg = <0xb90000 0x10000>;
|
|
clocks = <&chip_clk CLKID_GETH1>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
/* set by bootloader */
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
phy-connection-type = "mii";
|
|
phy-handle = <ðphy1>;
|
|
status = "disabled";
|
|
|
|
ethphy1: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
eth0: ethernet@e50000 {
|
|
compatible = "marvell,pxa168-eth";
|
|
reg = <0xe50000 0x10000>;
|
|
clocks = <&chip_clk CLKID_GETH0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
/* set by bootloader */
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
phy-connection-type = "mii";
|
|
phy-handle = <ðphy0>;
|
|
status = "disabled";
|
|
|
|
ethphy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
apb@e80000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0 0xe80000 0x10000>;
|
|
interrupt-parent = <&aic>;
|
|
|
|
gpio0: gpio@0400 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0x0400 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
porta: gpio-port@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
snps,nr-gpios = <8>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <0>;
|
|
};
|
|
};
|
|
|
|
gpio1: gpio@0800 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0x0800 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
portb: gpio-port@1 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
snps,nr-gpios = <8>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <1>;
|
|
};
|
|
};
|
|
|
|
gpio2: gpio@0c00 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0x0c00 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
portc: gpio-port@2 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
snps,nr-gpios = <8>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <2>;
|
|
};
|
|
};
|
|
|
|
gpio3: gpio@1000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0x1000 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
portd: gpio-port@3 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
snps,nr-gpios = <8>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <3>;
|
|
};
|
|
};
|
|
|
|
timer0: timer@2c00 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0x2c00 0x14>;
|
|
interrupts = <8>;
|
|
clocks = <&chip_clk CLKID_CFG>;
|
|
clock-names = "timer";
|
|
status = "okay";
|
|
};
|
|
|
|
timer1: timer@2c14 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0x2c14 0x14>;
|
|
interrupts = <9>;
|
|
clocks = <&chip_clk CLKID_CFG>;
|
|
clock-names = "timer";
|
|
status = "okay";
|
|
};
|
|
|
|
timer2: timer@2c28 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0x2c28 0x14>;
|
|
interrupts = <10>;
|
|
clocks = <&chip_clk CLKID_CFG>;
|
|
clock-names = "timer";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer3: timer@2c3c {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0x2c3c 0x14>;
|
|
interrupts = <11>;
|
|
clocks = <&chip_clk CLKID_CFG>;
|
|
clock-names = "timer";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer4: timer@2c50 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0x2c50 0x14>;
|
|
interrupts = <12>;
|
|
clocks = <&chip_clk CLKID_CFG>;
|
|
clock-names = "timer";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer5: timer@2c64 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0x2c64 0x14>;
|
|
interrupts = <13>;
|
|
clocks = <&chip_clk CLKID_CFG>;
|
|
clock-names = "timer";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer6: timer@2c78 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0x2c78 0x14>;
|
|
interrupts = <14>;
|
|
clocks = <&chip_clk CLKID_CFG>;
|
|
clock-names = "timer";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer7: timer@2c8c {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0x2c8c 0x14>;
|
|
interrupts = <15>;
|
|
clocks = <&chip_clk CLKID_CFG>;
|
|
clock-names = "timer";
|
|
status = "disabled";
|
|
};
|
|
|
|
aic: interrupt-controller@3000 {
|
|
compatible = "snps,dw-apb-ictl";
|
|
reg = <0x3000 0xc00>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
chip: chip-control@ea0000 {
|
|
compatible = "simple-mfd", "syscon";
|
|
reg = <0xea0000 0x400>;
|
|
|
|
chip_clk: clock {
|
|
compatible = "marvell,berlin2-clk";
|
|
#clock-cells = <1>;
|
|
clocks = <&refclk>;
|
|
clock-names = "refclk";
|
|
};
|
|
|
|
soc_pinctrl: pin-controller {
|
|
compatible = "marvell,berlin2cd-soc-pinctrl";
|
|
|
|
uart0_pmux: uart0-pmux {
|
|
groups = "G6";
|
|
function = "uart0";
|
|
};
|
|
};
|
|
|
|
chip_rst: reset {
|
|
compatible = "marvell,berlin2-reset";
|
|
#reset-cells = <2>;
|
|
};
|
|
};
|
|
|
|
usb0: usb@ed0000 {
|
|
compatible = "chipidea,usb2";
|
|
reg = <0xed0000 0x200>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&chip_clk CLKID_USB0>;
|
|
phys = <&usb_phy0>;
|
|
phy-names = "usb-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb1: usb@ee0000 {
|
|
compatible = "chipidea,usb2";
|
|
reg = <0xee0000 0x200>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&chip_clk CLKID_USB1>;
|
|
phys = <&usb_phy1>;
|
|
phy-names = "usb-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
apb@fc0000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0 0xfc0000 0x10000>;
|
|
interrupt-parent = <&sic>;
|
|
|
|
sm_gpio1: gpio@5000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0x5000 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
portf: gpio-port@5 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
snps,nr-gpios = <8>;
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
sm_gpio0: gpio@c000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xc000 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
porte: gpio-port@4 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
snps,nr-gpios = <8>;
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
uart0: serial@9000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x9000 0x100>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <1>;
|
|
interrupts = <8>;
|
|
clocks = <&refclk>;
|
|
pinctrl-0 = <&uart0_pmux>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@a000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xa000 0x100>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <1>;
|
|
interrupts = <9>;
|
|
clocks = <&refclk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sysctrl: system-controller@d000 {
|
|
compatible = "simple-mfd", "syscon";
|
|
reg = <0xd000 0x100>;
|
|
|
|
sys_pinctrl: pin-controller {
|
|
compatible = "marvell,berlin2cd-system-pinctrl";
|
|
};
|
|
};
|
|
|
|
sic: interrupt-controller@e000 {
|
|
compatible = "snps,dw-apb-ictl";
|
|
reg = <0xe000 0x400>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
};
|
|
};
|