mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 19:36:48 +07:00
4bb0d3ec3e
i386 Inline asm cleanup. Use cr/dr accessor functions.
Also, a potential bugfix. Also, some CR accessors really should be volatile.
Reads from CR0 (numeric state may change in an exception handler), writes to
CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction
re-ordering. I did not add memory clobber to CR3 / CR4 / CR0 updates, as it
was not there to begin with, and in no case should kernel memory be clobbered,
except when doing a TLB flush, which already has memory clobber.
I noticed that page invalidation does not have a memory clobber. I can't find
a bug as a result, but there is definitely a potential for a bug here:
#define __flush_tlb_single(addr) \
__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
Signed-off-by: Zachary Amsden <zach@vmware.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
151 lines
3.6 KiB
C
151 lines
3.6 KiB
C
/*
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* Suspend support specific for i386.
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*
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* Distribute under GPLv2
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*
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* Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
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* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/poll.h>
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#include <linux/delay.h>
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#include <linux/sysrq.h>
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#include <linux/proc_fs.h>
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#include <linux/irq.h>
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#include <linux/pm.h>
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#include <linux/device.h>
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#include <linux/suspend.h>
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#include <linux/acpi.h>
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#include <asm/uaccess.h>
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#include <asm/acpi.h>
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#include <asm/tlbflush.h>
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#include <asm/processor.h>
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static struct saved_context saved_context;
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unsigned long saved_context_ebx;
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unsigned long saved_context_esp, saved_context_ebp;
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unsigned long saved_context_esi, saved_context_edi;
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unsigned long saved_context_eflags;
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void __save_processor_state(struct saved_context *ctxt)
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{
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kernel_fpu_begin();
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/*
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* descriptor tables
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*/
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asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
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asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
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asm volatile ("str %0" : "=m" (ctxt->tr));
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/*
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* segment registers
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*/
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asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
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asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
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asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
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asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
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/*
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* control registers
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*/
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ctxt->cr0 = read_cr0();
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ctxt->cr2 = read_cr2();
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ctxt->cr3 = read_cr3();
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ctxt->cr4 = read_cr4();
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}
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void save_processor_state(void)
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{
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__save_processor_state(&saved_context);
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}
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static void
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do_fpu_end(void)
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{
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/* restore FPU regs if necessary */
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/* Do it out of line so that gcc does not move cr0 load to some stupid place */
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kernel_fpu_end();
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mxcsr_feature_mask_init();
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}
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static void fix_processor_context(void)
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{
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int cpu = smp_processor_id();
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struct tss_struct * t = &per_cpu(init_tss, cpu);
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set_tss_desc(cpu,t); /* This just modifies memory; should not be necessary. But... This is necessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
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per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_TSS].b &= 0xfffffdff;
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load_TR_desc(); /* This does ltr */
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load_LDT(¤t->active_mm->context); /* This does lldt */
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/*
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* Now maybe reload the debug registers
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*/
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if (current->thread.debugreg[7]){
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set_debugreg(current->thread.debugreg[0], 0);
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set_debugreg(current->thread.debugreg[1], 1);
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set_debugreg(current->thread.debugreg[2], 2);
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set_debugreg(current->thread.debugreg[3], 3);
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/* no 4 and 5 */
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set_debugreg(current->thread.debugreg[6], 6);
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set_debugreg(current->thread.debugreg[7], 7);
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}
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}
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void __restore_processor_state(struct saved_context *ctxt)
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{
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/*
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* control registers
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*/
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write_cr4(ctxt->cr4);
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write_cr3(ctxt->cr3);
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write_cr2(ctxt->cr2);
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write_cr2(ctxt->cr0);
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/*
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* now restore the descriptor tables to their proper values
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* ltr is done i fix_processor_context().
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*/
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asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
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asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));
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/*
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* segment registers
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*/
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asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
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asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
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asm volatile ("movw %0, %%gs" :: "r" (ctxt->gs));
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asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
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/*
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* sysenter MSRs
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*/
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if (boot_cpu_has(X86_FEATURE_SEP))
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enable_sep_cpu();
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fix_processor_context();
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do_fpu_end();
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mtrr_ap_init();
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}
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void restore_processor_state(void)
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{
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__restore_processor_state(&saved_context);
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}
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/* Needed by apm.c */
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EXPORT_SYMBOL(save_processor_state);
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EXPORT_SYMBOL(restore_processor_state);
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