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edabd38e1a
The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
/*
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* arch/arm/mach-dove/include/mach/pm.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_PM_H
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#define __ASM_ARCH_PM_H
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#include <asm/errno.h>
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#include <mach/irqs.h>
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#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
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#define CLOCK_GATING_USB0_MASK (1 << 0)
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#define CLOCK_GATING_USB1_MASK (1 << 1)
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#define CLOCK_GATING_GBE_MASK (1 << 2)
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#define CLOCK_GATING_SATA_MASK (1 << 3)
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#define CLOCK_GATING_PCIE0_MASK (1 << 4)
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#define CLOCK_GATING_PCIE1_MASK (1 << 5)
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#define CLOCK_GATING_SDIO0_MASK (1 << 8)
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#define CLOCK_GATING_SDIO1_MASK (1 << 9)
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#define CLOCK_GATING_NAND_MASK (1 << 10)
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#define CLOCK_GATING_CAMERA_MASK (1 << 11)
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#define CLOCK_GATING_I2S0_MASK (1 << 12)
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#define CLOCK_GATING_I2S1_MASK (1 << 13)
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#define CLOCK_GATING_CRYPTO_MASK (1 << 15)
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#define CLOCK_GATING_AC97_MASK (1 << 21)
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#define CLOCK_GATING_PDMA_MASK (1 << 22)
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#define CLOCK_GATING_XOR0_MASK (1 << 23)
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#define CLOCK_GATING_XOR1_MASK (1 << 24)
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#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30)
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#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
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#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)
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static inline int pmu_to_irq(int pin)
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{
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if (pin < NR_PMU_IRQS)
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return pin + IRQ_DOVE_PMU_START;
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return -EINVAL;
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}
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static inline int irq_to_pmu(int irq)
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{
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if (IRQ_DOVE_PMU_START < irq && irq < NR_IRQS)
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return irq - IRQ_DOVE_PMU_START;
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return -EINVAL;
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}
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#endif
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