mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ffbd523522
Specify Ethernet PHY IRQs in the Condor/V3HSK board device trees, now that we have the GPIO support (previously phylib had to resort to polling). Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
169 lines
2.8 KiB
Plaintext
169 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Condor board
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018 Cogent Embedded, Inc.
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*/
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/dts-v1/;
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#include "r8a77980.dtsi"
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/ {
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model = "Renesas Condor board based on r8a77980";
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compatible = "renesas,condor", "renesas,r8a77980";
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aliases {
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serial0 = &scif0;
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ethernet0 = &avb;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0 0x48000000 0 0x78000000>;
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};
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d3_3v: regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "D3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vddq_vin01: regulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "VDDQ_VIN01";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&avb {
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pinctrl-0 = <&avb_pins>;
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pinctrl-names = "default";
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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renesas,no-ether-link;
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status = "okay";
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio1>;
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interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&canfd {
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pinctrl-0 = <&canfd0_pins>;
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pinctrl-names = "default";
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status = "okay";
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channel0 {
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status = "okay";
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};
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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io_expander0: gpio@20 {
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compatible = "onnn,pca9654";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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io_expander1: gpio@21 {
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compatible = "onnn,pca9654";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&mmc0 {
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pinctrl-0 = <&mmc_pins>;
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pinctrl-1 = <&mmc_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&d3_3v>;
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vqmmc-supply = <&vddq_vin01>;
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mmc-hs200-1_8v;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&pfc {
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avb_pins: avb {
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groups = "avb_mdio", "avb_rgmii";
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function = "avb";
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};
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canfd0_pins: canfd0 {
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groups = "canfd0_data_a";
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function = "canfd0";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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mmc_pins: mmc {
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groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
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function = "mmc";
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power-source = <3300>;
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};
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mmc_pins_uhs: mmc_uhs {
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groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
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function = "mmc";
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power-source = <1800>;
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};
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scif0_pins: scif0 {
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groups = "scif0_data";
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function = "scif0";
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk_b";
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function = "scif_clk";
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};
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&scif_clk {
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clock-frequency = <14745600>;
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};
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