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684d984038
In memory Collection (IMC) counter pmu driver controls the ucode's
execution state. At the system boot, IMC perf driver pause the ucode.
Ucode state is changed to "running" only when any of the nest units
are monitored or profiled using perf tool.
Nest units support only limited set of hardware counters and ucode is
always programmed in the "production mode" ("accumulation") mode. This
mode is configured to provide key performance metric data for most of
the nest units.
But ucode also supports other modes which would be used for "debug" to
drill down specific nest units. That is, ucode when switched to
"powerbus" debug mode (for example), will dynamically reconfigure the
nest counters to target only "powerbus" related events in the hardware
counters. This allows the IMC nest unit to focus on powerbus related
transactions in the system in more detail. At this point, production
mode events may or may not be counted.
IMC nest counters has both in-band (ucode access) and out of band
access to it. Since not all nest counter configurations are supported
by ucode, out of band tools are used to characterize other nest
counter configurations.
Patch provides an interface via "debugfs" to enable the switching of
ucode modes in the system. To switch ucode mode, one has to first
pause the microcode (imc_cmd), and then write the target mode value to
the "imc_mode" file.
Proposed Approach:
In the proposed approach, the function (export_imc_mode_and_cmd) which
creates the debugfs interface for imc mode and command is implemented
in opal-imc.c. Thus we can use imc_get_mem_addr() to get the homer
base address for each chip.
The interface to expose imc mode and command is required only if we
have nest pmu units registered. Employing the existing data structures
to track whether we have any nest units registered will require to
extend data from perf side to opal-imc.c. Instead an integer is
introduced to hold that information by counting successful nest unit
registration. Debugfs interface is removed based on the integer count.
Example for the interface:
$ ls /sys/kernel/debug/imc
imc_cmd_0 imc_cmd_8 imc_mode_0 imc_mode_8
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
132 lines
3.0 KiB
C
132 lines
3.0 KiB
C
#ifndef __ASM_POWERPC_IMC_PMU_H
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#define __ASM_POWERPC_IMC_PMU_H
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/*
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* IMC Nest Performance Monitor counter support.
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*
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* Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
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* (C) 2017 Anju T Sudhakar, IBM Corporation.
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* (C) 2017 Hemant K Shaw, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or later version.
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*/
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#include <linux/perf_event.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include <asm/opal.h>
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/*
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* Compatibility macros for IMC devices
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*/
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#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters"
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#define IMC_DTB_UNIT_COMPAT "ibm,imc-counters"
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/*
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* LDBAR: Counter address and Enable/Disable macro.
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* perf/imc-pmu.c has the LDBAR layout information.
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*/
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#define THREAD_IMC_LDBAR_MASK 0x0003ffffffffe000ULL
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#define THREAD_IMC_ENABLE 0x8000000000000000ULL
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/*
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* For debugfs interface for imc-mode and imc-command
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*/
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#define IMC_CNTL_BLK_OFFSET 0x3FC00
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#define IMC_CNTL_BLK_CMD_OFFSET 8
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#define IMC_CNTL_BLK_MODE_OFFSET 32
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/*
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* Structure to hold memory address information for imc units.
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*/
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struct imc_mem_info {
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u64 *vbase;
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u32 id;
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};
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/*
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* Place holder for nest pmu events and values.
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*/
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struct imc_events {
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u32 value;
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char *name;
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char *unit;
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char *scale;
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};
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/* Event attribute array index */
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#define IMC_FORMAT_ATTR 0
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#define IMC_EVENT_ATTR 1
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#define IMC_CPUMASK_ATTR 2
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#define IMC_NULL_ATTR 3
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/* PMU Format attribute macros */
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#define IMC_EVENT_OFFSET_MASK 0xffffffffULL
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/*
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* Device tree parser code detects IMC pmu support and
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* registers new IMC pmus. This structure will hold the
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* pmu functions, events, counter memory information
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* and attrs for each imc pmu and will be referenced at
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* the time of pmu registration.
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*/
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struct imc_pmu {
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struct pmu pmu;
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struct imc_mem_info *mem_info;
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struct imc_events *events;
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/*
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* Attribute groups for the PMU. Slot 0 used for
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* format attribute, slot 1 used for cpusmask attribute,
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* slot 2 used for event attribute. Slot 3 keep as
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* NULL.
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*/
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const struct attribute_group *attr_groups[4];
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u32 counter_mem_size;
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int domain;
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/*
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* flag to notify whether the memory is mmaped
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* or allocated by kernel.
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*/
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bool imc_counter_mmaped;
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};
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/*
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* Structure to hold id, lock and reference count for the imc events which
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* are inited.
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*/
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struct imc_pmu_ref {
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struct mutex lock;
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unsigned int id;
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int refc;
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};
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/*
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* In-Memory Collection Counters type.
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* Data comes from Device tree.
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* Three device type are supported.
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*/
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enum {
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IMC_TYPE_THREAD = 0x1,
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IMC_TYPE_CORE = 0x4,
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IMC_TYPE_CHIP = 0x10,
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};
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/*
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* Domains for IMC PMUs
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*/
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#define IMC_DOMAIN_NEST 1
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#define IMC_DOMAIN_CORE 2
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#define IMC_DOMAIN_THREAD 3
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extern int init_imc_pmu(struct device_node *parent,
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struct imc_pmu *pmu_ptr, int pmu_id);
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extern void thread_imc_disable(void);
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extern int get_max_nest_dev(void);
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#endif /* __ASM_POWERPC_IMC_PMU_H */
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