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e5eaa7cc0c
An upcoming change in the hmm_range_register API requires passing in a pointer to an hmm_mirror instead of mm_struct. To access the hmm_mirror we need pass bo instead of ttm to amdgpu_ttm_tt_get_user_pages because mirror is part of amdgpu_mn structure, which is accessible from bo. v2: fix building without CONFIG_HMM_MIRROR (Arnd) Signed-off-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
135 lines
4.8 KiB
C
135 lines
4.8 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_TTM_H__
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#define __AMDGPU_TTM_H__
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#include "amdgpu.h"
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#include <drm/gpu_scheduler.h>
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#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
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#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
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#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
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#define AMDGPU_PL_FLAG_GDS (TTM_PL_FLAG_PRIV << 0)
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#define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
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#define AMDGPU_PL_FLAG_OA (TTM_PL_FLAG_PRIV << 2)
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#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
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#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
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struct amdgpu_mman {
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struct ttm_bo_device bdev;
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bool mem_global_referenced;
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bool initialized;
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void __iomem *aper_base_kaddr;
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#if defined(CONFIG_DEBUG_FS)
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struct dentry *debugfs_entries[8];
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#endif
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/* buffer handling */
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const struct amdgpu_buffer_funcs *buffer_funcs;
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struct amdgpu_ring *buffer_funcs_ring;
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bool buffer_funcs_enabled;
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struct mutex gtt_window_lock;
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/* Scheduler entity for buffer moves */
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struct drm_sched_entity entity;
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};
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struct amdgpu_copy_mem {
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struct ttm_buffer_object *bo;
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struct ttm_mem_reg *mem;
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unsigned long offset;
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};
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extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
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extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
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bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
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uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
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int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
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u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
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uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
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uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
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int amdgpu_ttm_init(struct amdgpu_device *adev);
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void amdgpu_ttm_late_init(struct amdgpu_device *adev);
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void amdgpu_ttm_fini(struct amdgpu_device *adev);
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void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
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bool enable);
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int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
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uint64_t dst_offset, uint32_t byte_count,
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struct reservation_object *resv,
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struct dma_fence **fence, bool direct_submit,
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bool vm_needs_flush);
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int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
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struct amdgpu_copy_mem *src,
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struct amdgpu_copy_mem *dst,
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uint64_t size,
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struct reservation_object *resv,
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struct dma_fence **f);
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int amdgpu_fill_buffer(struct amdgpu_bo *bo,
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uint32_t src_data,
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struct reservation_object *resv,
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struct dma_fence **fence);
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int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
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int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
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int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
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#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
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int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages);
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bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
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#else
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static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
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struct page **pages)
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{
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return -EPERM;
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}
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static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
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{
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return false;
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}
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#endif
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void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
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int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
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uint32_t flags);
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bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
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struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
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bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
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unsigned long end);
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bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
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int *last_invalidated);
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bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
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bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
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uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
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uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
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struct ttm_mem_reg *mem);
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#endif
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