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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4ab1586488
Check CPUID leaves for all the Resource Director Technology (RDT) Cache Allocation Technology (CAT) bits. Presence of allocation features: CPUID.(EAX=7H, ECX=0):EBX[bit 15] X86_FEATURE_RDT_A L2 and L3 caches are each separately enabled: CPUID.(EAX=10H, ECX=0):EBX[bit 1] X86_FEATURE_CAT_L3 CPUID.(EAX=10H, ECX=0):EBX[bit 2] X86_FEATURE_CAT_L2 L3 cache may support independent control of allocation for code and data (CDP = Code/Data Prioritization): CPUID.(EAX=10H, ECX=1):ECX[bit 2] X86_FEATURE_CDP_L3 [ tglx: Fixed up Borislavs comments and moved the feature bits into a gap ] Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Acked-by: "Borislav Petkov" <bp@suse.de> Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com> Cc: "Tony Luck" <tony.luck@intel.com> Cc: "David Carrillo-Cisneros" <davidcc@google.com> Cc: "Sai Prakhya" <sai.praneeth.prakhya@intel.com> Cc: "Peter Zijlstra" <peterz@infradead.org> Cc: "Stephane Eranian" <eranian@google.com> Cc: "Dave Hansen" <dave.hansen@intel.com> Cc: "Shaohua Li" <shli@fb.com> Cc: "Nilay Vaish" <nilayvaish@gmail.com> Cc: "Vikas Shivappa" <vikas.shivappa@linux.intel.com> Cc: "Ingo Molnar" <mingo@elte.hu> Cc: "H. Peter Anvin" <h.peter.anvin@intel.com> Link: http://lkml.kernel.org/r/1477142405-32078-5-git-send-email-fenghua.yu@intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
63 lines
1.5 KiB
C
63 lines
1.5 KiB
C
/*
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* Routines to identify additional cpu features that are scattered in
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* cpuid space.
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*/
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#include <linux/cpu.h>
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#include <asm/pat.h>
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#include <asm/processor.h>
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#include <asm/apic.h>
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struct cpuid_bit {
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u16 feature;
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u8 reg;
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u8 bit;
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u32 level;
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u32 sub_leaf;
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};
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enum cpuid_regs {
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CR_EAX = 0,
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CR_ECX,
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CR_EDX,
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CR_EBX
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};
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void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
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{
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u32 max_level;
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u32 regs[4];
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const struct cpuid_bit *cb;
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static const struct cpuid_bit cpuid_bits[] = {
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{ X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 },
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{ X86_FEATURE_AVX512_4VNNIW, CR_EDX, 2, 0x00000007, 0 },
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{ X86_FEATURE_AVX512_4FMAPS, CR_EDX, 3, 0x00000007, 0 },
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{ X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 },
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{ X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 },
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{ X86_FEATURE_CAT_L3, CR_EBX, 1, 0x00000010, 0 },
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{ X86_FEATURE_CAT_L2, CR_EBX, 2, 0x00000010, 0 },
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{ X86_FEATURE_CDP_L3, CR_ECX, 2, 0x00000010, 1 },
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{ X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 },
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{ X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 },
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{ X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 },
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{ 0, 0, 0, 0, 0 }
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};
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for (cb = cpuid_bits; cb->feature; cb++) {
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/* Verify that the level is valid */
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max_level = cpuid_eax(cb->level & 0xffff0000);
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if (max_level < cb->level ||
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max_level > (cb->level | 0xffff))
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continue;
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cpuid_count(cb->level, cb->sub_leaf, ®s[CR_EAX],
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®s[CR_EBX], ®s[CR_ECX], ®s[CR_EDX]);
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if (regs[cb->reg] & (1 << cb->bit))
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set_cpu_cap(c, cb->feature);
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}
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}
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