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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2eb167293f
They will be used for JPEG2.0 and later. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
212 lines
5.1 KiB
C
212 lines
5.1 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_jpeg.h"
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#include "amdgpu_pm.h"
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#include "soc15d.h"
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#include "soc15_common.h"
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#define JPEG_IDLE_TIMEOUT msecs_to_jiffies(1000)
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static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
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int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
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{
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INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
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return 0;
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}
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int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
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{
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int i;
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cancel_delayed_work_sync(&adev->jpeg.idle_work);
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec);
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}
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return 0;
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}
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int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
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{
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cancel_delayed_work_sync(&adev->jpeg.idle_work);
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return 0;
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}
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int amdgpu_jpeg_resume(struct amdgpu_device *adev)
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{
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return 0;
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}
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static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
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{
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struct amdgpu_device *adev =
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container_of(work, struct amdgpu_device, jpeg.idle_work.work);
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unsigned int fences = 0;
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unsigned int i;
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec);
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}
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if (fences == 0)
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
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AMD_PG_STATE_GATE);
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else
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schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
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}
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void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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bool set_clocks = !cancel_delayed_work_sync(&adev->jpeg.idle_work);
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if (set_clocks)
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
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AMD_PG_STATE_UNGATE);
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}
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void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
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{
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schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
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}
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int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t tmp = 0;
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unsigned i;
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int r;
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WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
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r = amdgpu_ring_alloc(ring, 3);
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if (r)
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return r;
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amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch, 0));
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amdgpu_ring_write(ring, 0xDEADBEEF);
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amdgpu_ring_commit(ring);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
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if (tmp == 0xDEADBEEF)
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break;
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udelay(1);
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}
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if (i >= adev->usec_timeout)
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r = -ETIMEDOUT;
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return r;
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}
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static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
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struct dma_fence **fence)
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_job *job;
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struct amdgpu_ib *ib;
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struct dma_fence *f = NULL;
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const unsigned ib_size_dw = 16;
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int i, r;
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r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
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if (r)
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return r;
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ib = &job->ibs[0];
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ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
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ib->ptr[1] = 0xDEADBEEF;
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for (i = 2; i < 16; i += 2) {
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ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
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ib->ptr[i+1] = 0;
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}
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ib->length_dw = 16;
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r = amdgpu_job_submit_direct(job, ring, &f);
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if (r)
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goto err;
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if (fence)
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*fence = dma_fence_get(f);
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dma_fence_put(f);
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return 0;
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err:
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amdgpu_job_free(job);
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return r;
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}
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int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t tmp = 0;
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unsigned i;
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struct dma_fence *fence = NULL;
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long r = 0;
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r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
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if (r)
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goto error;
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r = dma_fence_wait_timeout(fence, false, timeout);
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if (r == 0) {
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r = -ETIMEDOUT;
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goto error;
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} else if (r < 0) {
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goto error;
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} else {
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r = 0;
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}
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
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if (tmp == 0xDEADBEEF)
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break;
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udelay(1);
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}
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if (i >= adev->usec_timeout)
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r = -ETIMEDOUT;
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dma_fence_put(fence);
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error:
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return r;
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}
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