mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dea7e0ac45
ttm tt rework modified the way we allocate and populate the ttm_tt structure, the AGP side was missing some bit to properly work. Fix those and fix radeon and nouveau AGP support. Tested on radeon only so far. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
913 lines
24 KiB
C
913 lines
24 KiB
C
/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Dave Airlie
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*/
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#include <ttm/ttm_bo_api.h>
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#include <ttm/ttm_bo_driver.h>
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#include <ttm/ttm_placement.h>
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#include <ttm/ttm_module.h>
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#include <ttm/ttm_page_alloc.h>
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
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static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
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static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
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{
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struct radeon_mman *mman;
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struct radeon_device *rdev;
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mman = container_of(bdev, struct radeon_mman, bdev);
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rdev = container_of(mman, struct radeon_device, mman);
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return rdev;
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}
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/*
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* Global memory.
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*/
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static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
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{
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return ttm_mem_global_init(ref->object);
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}
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static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
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{
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ttm_mem_global_release(ref->object);
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}
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static int radeon_ttm_global_init(struct radeon_device *rdev)
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{
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struct drm_global_reference *global_ref;
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int r;
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rdev->mman.mem_global_referenced = false;
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global_ref = &rdev->mman.mem_global_ref;
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global_ref->global_type = DRM_GLOBAL_TTM_MEM;
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global_ref->size = sizeof(struct ttm_mem_global);
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global_ref->init = &radeon_ttm_mem_global_init;
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global_ref->release = &radeon_ttm_mem_global_release;
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r = drm_global_item_ref(global_ref);
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if (r != 0) {
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DRM_ERROR("Failed setting up TTM memory accounting "
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"subsystem.\n");
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return r;
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}
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rdev->mman.bo_global_ref.mem_glob =
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rdev->mman.mem_global_ref.object;
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global_ref = &rdev->mman.bo_global_ref.ref;
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global_ref->global_type = DRM_GLOBAL_TTM_BO;
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global_ref->size = sizeof(struct ttm_bo_global);
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global_ref->init = &ttm_bo_global_init;
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global_ref->release = &ttm_bo_global_release;
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r = drm_global_item_ref(global_ref);
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if (r != 0) {
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DRM_ERROR("Failed setting up TTM BO subsystem.\n");
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drm_global_item_unref(&rdev->mman.mem_global_ref);
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return r;
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}
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rdev->mman.mem_global_referenced = true;
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return 0;
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}
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static void radeon_ttm_global_fini(struct radeon_device *rdev)
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{
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if (rdev->mman.mem_global_referenced) {
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drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
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drm_global_item_unref(&rdev->mman.mem_global_ref);
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rdev->mman.mem_global_referenced = false;
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}
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}
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static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
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{
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return 0;
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}
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static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
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struct ttm_mem_type_manager *man)
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{
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struct radeon_device *rdev;
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rdev = radeon_get_rdev(bdev);
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switch (type) {
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case TTM_PL_SYSTEM:
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/* System memory */
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_MASK_CACHING;
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man->default_caching = TTM_PL_FLAG_CACHED;
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break;
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case TTM_PL_TT:
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man->func = &ttm_bo_manager_func;
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man->gpu_offset = rdev->mc.gtt_start;
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man->available_caching = TTM_PL_MASK_CACHING;
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man->default_caching = TTM_PL_FLAG_CACHED;
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
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#if __OS_HAS_AGP
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if (rdev->flags & RADEON_IS_AGP) {
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if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
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DRM_ERROR("AGP is not enabled for memory type %u\n",
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(unsigned)type);
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return -EINVAL;
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}
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if (!rdev->ddev->agp->cant_use_aperture)
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_WC;
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man->default_caching = TTM_PL_FLAG_WC;
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}
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#endif
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break;
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case TTM_PL_VRAM:
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/* "On-card" video ram */
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man->func = &ttm_bo_manager_func;
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man->gpu_offset = rdev->mc.vram_start;
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man->flags = TTM_MEMTYPE_FLAG_FIXED |
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TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
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man->default_caching = TTM_PL_FLAG_WC;
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break;
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default:
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DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
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return -EINVAL;
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}
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return 0;
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}
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static void radeon_evict_flags(struct ttm_buffer_object *bo,
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struct ttm_placement *placement)
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{
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struct radeon_bo *rbo;
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static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
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if (!radeon_ttm_bo_is_radeon_bo(bo)) {
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placement->fpfn = 0;
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placement->lpfn = 0;
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placement->placement = &placements;
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placement->busy_placement = &placements;
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placement->num_placement = 1;
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placement->num_busy_placement = 1;
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return;
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}
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rbo = container_of(bo, struct radeon_bo, tbo);
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switch (bo->mem.mem_type) {
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case TTM_PL_VRAM:
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if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
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radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
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else
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radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
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break;
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case TTM_PL_TT:
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default:
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radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
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}
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*placement = rbo->placement;
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}
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static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
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{
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return 0;
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}
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static void radeon_move_null(struct ttm_buffer_object *bo,
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struct ttm_mem_reg *new_mem)
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{
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struct ttm_mem_reg *old_mem = &bo->mem;
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BUG_ON(old_mem->mm_node != NULL);
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*old_mem = *new_mem;
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new_mem->mm_node = NULL;
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}
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static int radeon_move_blit(struct ttm_buffer_object *bo,
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bool evict, int no_wait_reserve, bool no_wait_gpu,
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struct ttm_mem_reg *new_mem,
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struct ttm_mem_reg *old_mem)
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{
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struct radeon_device *rdev;
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uint64_t old_start, new_start;
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struct radeon_fence *fence;
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int r, i;
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rdev = radeon_get_rdev(bo->bdev);
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r = radeon_fence_create(rdev, &fence, rdev->copy_ring);
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if (unlikely(r)) {
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return r;
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}
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old_start = old_mem->start << PAGE_SHIFT;
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new_start = new_mem->start << PAGE_SHIFT;
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switch (old_mem->mem_type) {
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case TTM_PL_VRAM:
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old_start += rdev->mc.vram_start;
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break;
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case TTM_PL_TT:
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old_start += rdev->mc.gtt_start;
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break;
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default:
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DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
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return -EINVAL;
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}
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switch (new_mem->mem_type) {
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case TTM_PL_VRAM:
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new_start += rdev->mc.vram_start;
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break;
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case TTM_PL_TT:
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new_start += rdev->mc.gtt_start;
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break;
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default:
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DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
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return -EINVAL;
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}
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if (!rdev->ring[rdev->copy_ring].ready) {
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DRM_ERROR("Trying to move memory with ring turned off.\n");
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return -EINVAL;
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}
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BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
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/* sync other rings */
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if (rdev->family >= CHIP_R600) {
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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/* no need to sync to our own or unused rings */
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if (i == rdev->copy_ring || !rdev->ring[i].ready)
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continue;
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if (!fence->semaphore) {
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r = radeon_semaphore_create(rdev, &fence->semaphore);
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/* FIXME: handle semaphore error */
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if (r)
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continue;
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}
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r = radeon_ring_lock(rdev, &rdev->ring[i], 3);
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/* FIXME: handle ring lock error */
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if (r)
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continue;
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radeon_semaphore_emit_signal(rdev, i, fence->semaphore);
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radeon_ring_unlock_commit(rdev, &rdev->ring[i]);
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r = radeon_ring_lock(rdev, &rdev->ring[rdev->copy_ring], 3);
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/* FIXME: handle ring lock error */
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if (r)
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continue;
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radeon_semaphore_emit_wait(rdev, rdev->copy_ring, fence->semaphore);
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radeon_ring_unlock_commit(rdev, &rdev->ring[rdev->copy_ring]);
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}
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}
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r = radeon_copy(rdev, old_start, new_start,
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new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
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fence);
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/* FIXME: handle copy error */
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r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
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evict, no_wait_reserve, no_wait_gpu, new_mem);
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radeon_fence_unref(&fence);
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return r;
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}
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static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
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bool evict, bool interruptible,
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bool no_wait_reserve, bool no_wait_gpu,
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struct ttm_mem_reg *new_mem)
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{
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struct radeon_device *rdev;
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struct ttm_mem_reg *old_mem = &bo->mem;
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struct ttm_mem_reg tmp_mem;
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u32 placements;
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struct ttm_placement placement;
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int r;
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rdev = radeon_get_rdev(bo->bdev);
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tmp_mem = *new_mem;
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tmp_mem.mm_node = NULL;
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placement.fpfn = 0;
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placement.lpfn = 0;
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placement.num_placement = 1;
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placement.placement = &placements;
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placement.num_busy_placement = 1;
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placement.busy_placement = &placements;
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placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
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r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
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interruptible, no_wait_reserve, no_wait_gpu);
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if (unlikely(r)) {
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return r;
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}
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r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
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if (unlikely(r)) {
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goto out_cleanup;
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}
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r = ttm_tt_bind(bo->ttm, &tmp_mem);
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if (unlikely(r)) {
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goto out_cleanup;
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}
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r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem);
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if (unlikely(r)) {
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goto out_cleanup;
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}
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r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
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out_cleanup:
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ttm_bo_mem_put(bo, &tmp_mem);
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return r;
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}
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static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
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bool evict, bool interruptible,
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bool no_wait_reserve, bool no_wait_gpu,
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struct ttm_mem_reg *new_mem)
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{
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struct radeon_device *rdev;
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struct ttm_mem_reg *old_mem = &bo->mem;
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struct ttm_mem_reg tmp_mem;
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struct ttm_placement placement;
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u32 placements;
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int r;
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rdev = radeon_get_rdev(bo->bdev);
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tmp_mem = *new_mem;
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tmp_mem.mm_node = NULL;
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placement.fpfn = 0;
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placement.lpfn = 0;
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placement.num_placement = 1;
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placement.placement = &placements;
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placement.num_busy_placement = 1;
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placement.busy_placement = &placements;
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placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
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r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu);
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if (unlikely(r)) {
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return r;
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}
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r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
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if (unlikely(r)) {
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goto out_cleanup;
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}
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r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
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if (unlikely(r)) {
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goto out_cleanup;
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}
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out_cleanup:
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ttm_bo_mem_put(bo, &tmp_mem);
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return r;
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}
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|
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static int radeon_bo_move(struct ttm_buffer_object *bo,
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bool evict, bool interruptible,
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bool no_wait_reserve, bool no_wait_gpu,
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struct ttm_mem_reg *new_mem)
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{
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struct radeon_device *rdev;
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struct ttm_mem_reg *old_mem = &bo->mem;
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int r;
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rdev = radeon_get_rdev(bo->bdev);
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if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
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radeon_move_null(bo, new_mem);
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return 0;
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}
|
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if ((old_mem->mem_type == TTM_PL_TT &&
|
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new_mem->mem_type == TTM_PL_SYSTEM) ||
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(old_mem->mem_type == TTM_PL_SYSTEM &&
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new_mem->mem_type == TTM_PL_TT)) {
|
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/* bind is enough */
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radeon_move_null(bo, new_mem);
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return 0;
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}
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if (!rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready || rdev->asic->copy == NULL) {
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/* use memcpy */
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goto memcpy;
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}
|
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|
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if (old_mem->mem_type == TTM_PL_VRAM &&
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new_mem->mem_type == TTM_PL_SYSTEM) {
|
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r = radeon_move_vram_ram(bo, evict, interruptible,
|
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no_wait_reserve, no_wait_gpu, new_mem);
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} else if (old_mem->mem_type == TTM_PL_SYSTEM &&
|
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new_mem->mem_type == TTM_PL_VRAM) {
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r = radeon_move_ram_vram(bo, evict, interruptible,
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no_wait_reserve, no_wait_gpu, new_mem);
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} else {
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r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
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}
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if (r) {
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memcpy:
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r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
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}
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return r;
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}
|
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|
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static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
|
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{
|
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struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
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struct radeon_device *rdev = radeon_get_rdev(bdev);
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|
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mem->bus.addr = NULL;
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mem->bus.offset = 0;
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mem->bus.size = mem->num_pages << PAGE_SHIFT;
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mem->bus.base = 0;
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mem->bus.is_iomem = false;
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if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
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return -EINVAL;
|
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switch (mem->mem_type) {
|
|
case TTM_PL_SYSTEM:
|
|
/* system memory */
|
|
return 0;
|
|
case TTM_PL_TT:
|
|
#if __OS_HAS_AGP
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
/* RADEON_IS_AGP is set only if AGP is active */
|
|
mem->bus.offset = mem->start << PAGE_SHIFT;
|
|
mem->bus.base = rdev->mc.agp_base;
|
|
mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
|
|
}
|
|
#endif
|
|
break;
|
|
case TTM_PL_VRAM:
|
|
mem->bus.offset = mem->start << PAGE_SHIFT;
|
|
/* check if it's visible */
|
|
if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
|
|
return -EINVAL;
|
|
mem->bus.base = rdev->mc.aper_base;
|
|
mem->bus.is_iomem = true;
|
|
#ifdef __alpha__
|
|
/*
|
|
* Alpha: use bus.addr to hold the ioremap() return,
|
|
* so we can modify bus.base below.
|
|
*/
|
|
if (mem->placement & TTM_PL_FLAG_WC)
|
|
mem->bus.addr =
|
|
ioremap_wc(mem->bus.base + mem->bus.offset,
|
|
mem->bus.size);
|
|
else
|
|
mem->bus.addr =
|
|
ioremap_nocache(mem->bus.base + mem->bus.offset,
|
|
mem->bus.size);
|
|
|
|
/*
|
|
* Alpha: Use just the bus offset plus
|
|
* the hose/domain memory base for bus.base.
|
|
* It then can be used to build PTEs for VRAM
|
|
* access, as done in ttm_bo_vm_fault().
|
|
*/
|
|
mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
|
|
rdev->ddev->hose->dense_mem_base;
|
|
#endif
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
|
|
{
|
|
}
|
|
|
|
static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
|
|
bool lazy, bool interruptible)
|
|
{
|
|
return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
|
|
}
|
|
|
|
static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void radeon_sync_obj_unref(void **sync_obj)
|
|
{
|
|
radeon_fence_unref((struct radeon_fence **)sync_obj);
|
|
}
|
|
|
|
static void *radeon_sync_obj_ref(void *sync_obj)
|
|
{
|
|
return radeon_fence_ref((struct radeon_fence *)sync_obj);
|
|
}
|
|
|
|
static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
|
|
{
|
|
return radeon_fence_signaled((struct radeon_fence *)sync_obj);
|
|
}
|
|
|
|
/*
|
|
* TTM backend functions.
|
|
*/
|
|
struct radeon_ttm_tt {
|
|
struct ttm_dma_tt ttm;
|
|
struct radeon_device *rdev;
|
|
u64 offset;
|
|
};
|
|
|
|
static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
|
|
struct ttm_mem_reg *bo_mem)
|
|
{
|
|
struct radeon_ttm_tt *gtt = (void*)ttm;
|
|
int r;
|
|
|
|
gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
|
|
if (!ttm->num_pages) {
|
|
WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
|
|
ttm->num_pages, bo_mem, ttm);
|
|
}
|
|
r = radeon_gart_bind(gtt->rdev, gtt->offset,
|
|
ttm->num_pages, ttm->pages, gtt->ttm.dma_address);
|
|
if (r) {
|
|
DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
|
|
ttm->num_pages, (unsigned)gtt->offset);
|
|
return r;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
|
|
{
|
|
struct radeon_ttm_tt *gtt = (void *)ttm;
|
|
|
|
radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
|
|
return 0;
|
|
}
|
|
|
|
static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
|
|
{
|
|
struct radeon_ttm_tt *gtt = (void *)ttm;
|
|
|
|
ttm_dma_tt_fini(>t->ttm);
|
|
kfree(gtt);
|
|
}
|
|
|
|
static struct ttm_backend_func radeon_backend_func = {
|
|
.bind = &radeon_ttm_backend_bind,
|
|
.unbind = &radeon_ttm_backend_unbind,
|
|
.destroy = &radeon_ttm_backend_destroy,
|
|
};
|
|
|
|
struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
|
|
unsigned long size, uint32_t page_flags,
|
|
struct page *dummy_read_page)
|
|
{
|
|
struct radeon_device *rdev;
|
|
struct radeon_ttm_tt *gtt;
|
|
|
|
rdev = radeon_get_rdev(bdev);
|
|
#if __OS_HAS_AGP
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
|
|
size, page_flags, dummy_read_page);
|
|
}
|
|
#endif
|
|
|
|
gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
|
|
if (gtt == NULL) {
|
|
return NULL;
|
|
}
|
|
gtt->ttm.ttm.func = &radeon_backend_func;
|
|
gtt->rdev = rdev;
|
|
if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
|
|
kfree(gtt);
|
|
return NULL;
|
|
}
|
|
return >t->ttm.ttm;
|
|
}
|
|
|
|
static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
|
|
{
|
|
struct radeon_device *rdev;
|
|
struct radeon_ttm_tt *gtt = (void *)ttm;
|
|
unsigned i;
|
|
int r;
|
|
|
|
if (ttm->state != tt_unpopulated)
|
|
return 0;
|
|
|
|
rdev = radeon_get_rdev(ttm->bdev);
|
|
#if __OS_HAS_AGP
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
return ttm_agp_tt_populate(ttm);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
if (swiotlb_nr_tbl()) {
|
|
return ttm_dma_populate(>t->ttm, rdev->dev);
|
|
}
|
|
#endif
|
|
|
|
r = ttm_pool_populate(ttm);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
for (i = 0; i < ttm->num_pages; i++) {
|
|
gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
|
|
0, PAGE_SIZE,
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
|
|
while (--i) {
|
|
pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
gtt->ttm.dma_address[i] = 0;
|
|
}
|
|
ttm_pool_unpopulate(ttm);
|
|
return -EFAULT;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
|
|
{
|
|
struct radeon_device *rdev;
|
|
struct radeon_ttm_tt *gtt = (void *)ttm;
|
|
unsigned i;
|
|
|
|
rdev = radeon_get_rdev(ttm->bdev);
|
|
#if __OS_HAS_AGP
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
ttm_agp_tt_unpopulate(ttm);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
if (swiotlb_nr_tbl()) {
|
|
ttm_dma_unpopulate(>t->ttm, rdev->dev);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
for (i = 0; i < ttm->num_pages; i++) {
|
|
if (gtt->ttm.dma_address[i]) {
|
|
pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
}
|
|
}
|
|
|
|
ttm_pool_unpopulate(ttm);
|
|
}
|
|
|
|
static struct ttm_bo_driver radeon_bo_driver = {
|
|
.ttm_tt_create = &radeon_ttm_tt_create,
|
|
.ttm_tt_populate = &radeon_ttm_tt_populate,
|
|
.ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
|
|
.invalidate_caches = &radeon_invalidate_caches,
|
|
.init_mem_type = &radeon_init_mem_type,
|
|
.evict_flags = &radeon_evict_flags,
|
|
.move = &radeon_bo_move,
|
|
.verify_access = &radeon_verify_access,
|
|
.sync_obj_signaled = &radeon_sync_obj_signaled,
|
|
.sync_obj_wait = &radeon_sync_obj_wait,
|
|
.sync_obj_flush = &radeon_sync_obj_flush,
|
|
.sync_obj_unref = &radeon_sync_obj_unref,
|
|
.sync_obj_ref = &radeon_sync_obj_ref,
|
|
.move_notify = &radeon_bo_move_notify,
|
|
.fault_reserve_notify = &radeon_bo_fault_reserve_notify,
|
|
.io_mem_reserve = &radeon_ttm_io_mem_reserve,
|
|
.io_mem_free = &radeon_ttm_io_mem_free,
|
|
};
|
|
|
|
int radeon_ttm_init(struct radeon_device *rdev)
|
|
{
|
|
int r;
|
|
|
|
r = radeon_ttm_global_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
/* No others user of address space so set it to 0 */
|
|
r = ttm_bo_device_init(&rdev->mman.bdev,
|
|
rdev->mman.bo_global_ref.ref.object,
|
|
&radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
|
|
rdev->need_dma32);
|
|
if (r) {
|
|
DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
|
|
return r;
|
|
}
|
|
rdev->mman.initialized = true;
|
|
r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
|
|
rdev->mc.real_vram_size >> PAGE_SHIFT);
|
|
if (r) {
|
|
DRM_ERROR("Failed initializing VRAM heap.\n");
|
|
return r;
|
|
}
|
|
r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
|
|
RADEON_GEM_DOMAIN_VRAM,
|
|
&rdev->stollen_vga_memory);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
|
|
if (r)
|
|
return r;
|
|
r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
|
|
radeon_bo_unreserve(rdev->stollen_vga_memory);
|
|
if (r) {
|
|
radeon_bo_unref(&rdev->stollen_vga_memory);
|
|
return r;
|
|
}
|
|
DRM_INFO("radeon: %uM of VRAM memory ready\n",
|
|
(unsigned)rdev->mc.real_vram_size / (1024 * 1024));
|
|
r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
|
|
rdev->mc.gtt_size >> PAGE_SHIFT);
|
|
if (r) {
|
|
DRM_ERROR("Failed initializing GTT heap.\n");
|
|
return r;
|
|
}
|
|
DRM_INFO("radeon: %uM of GTT memory ready.\n",
|
|
(unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
|
|
if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
|
|
rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
|
|
}
|
|
|
|
r = radeon_ttm_debugfs_init(rdev);
|
|
if (r) {
|
|
DRM_ERROR("Failed to init debugfs\n");
|
|
return r;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void radeon_ttm_fini(struct radeon_device *rdev)
|
|
{
|
|
int r;
|
|
|
|
if (!rdev->mman.initialized)
|
|
return;
|
|
if (rdev->stollen_vga_memory) {
|
|
r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
|
|
if (r == 0) {
|
|
radeon_bo_unpin(rdev->stollen_vga_memory);
|
|
radeon_bo_unreserve(rdev->stollen_vga_memory);
|
|
}
|
|
radeon_bo_unref(&rdev->stollen_vga_memory);
|
|
}
|
|
ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
|
|
ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
|
|
ttm_bo_device_release(&rdev->mman.bdev);
|
|
radeon_gart_fini(rdev);
|
|
radeon_ttm_global_fini(rdev);
|
|
rdev->mman.initialized = false;
|
|
DRM_INFO("radeon: ttm finalized\n");
|
|
}
|
|
|
|
/* this should only be called at bootup or when userspace
|
|
* isn't running */
|
|
void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
|
|
{
|
|
struct ttm_mem_type_manager *man;
|
|
|
|
if (!rdev->mman.initialized)
|
|
return;
|
|
|
|
man = &rdev->mman.bdev.man[TTM_PL_VRAM];
|
|
/* this just adjusts TTM size idea, which sets lpfn to the correct value */
|
|
man->size = size >> PAGE_SHIFT;
|
|
}
|
|
|
|
static struct vm_operations_struct radeon_ttm_vm_ops;
|
|
static const struct vm_operations_struct *ttm_vm_ops = NULL;
|
|
|
|
static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
|
|
{
|
|
struct ttm_buffer_object *bo;
|
|
struct radeon_device *rdev;
|
|
int r;
|
|
|
|
bo = (struct ttm_buffer_object *)vma->vm_private_data;
|
|
if (bo == NULL) {
|
|
return VM_FAULT_NOPAGE;
|
|
}
|
|
rdev = radeon_get_rdev(bo->bdev);
|
|
mutex_lock(&rdev->vram_mutex);
|
|
r = ttm_vm_ops->fault(vma, vmf);
|
|
mutex_unlock(&rdev->vram_mutex);
|
|
return r;
|
|
}
|
|
|
|
int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
|
|
{
|
|
struct drm_file *file_priv;
|
|
struct radeon_device *rdev;
|
|
int r;
|
|
|
|
if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
|
|
return drm_mmap(filp, vma);
|
|
}
|
|
|
|
file_priv = filp->private_data;
|
|
rdev = file_priv->minor->dev->dev_private;
|
|
if (rdev == NULL) {
|
|
return -EINVAL;
|
|
}
|
|
r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
|
|
if (unlikely(r != 0)) {
|
|
return r;
|
|
}
|
|
if (unlikely(ttm_vm_ops == NULL)) {
|
|
ttm_vm_ops = vma->vm_ops;
|
|
radeon_ttm_vm_ops = *ttm_vm_ops;
|
|
radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
|
|
}
|
|
vma->vm_ops = &radeon_ttm_vm_ops;
|
|
return 0;
|
|
}
|
|
|
|
|
|
#define RADEON_DEBUGFS_MEM_TYPES 2
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
static int radeon_mm_dump_table(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
int ret;
|
|
struct ttm_bo_global *glob = rdev->mman.bdev.glob;
|
|
|
|
spin_lock(&glob->lru_lock);
|
|
ret = drm_mm_dump_table(m, mm);
|
|
spin_unlock(&glob->lru_lock);
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2];
|
|
static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32];
|
|
unsigned i;
|
|
|
|
for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
|
|
if (i == 0)
|
|
sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
|
|
else
|
|
sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
|
|
radeon_mem_types_list[i].name = radeon_mem_types_names[i];
|
|
radeon_mem_types_list[i].show = &radeon_mm_dump_table;
|
|
radeon_mem_types_list[i].driver_features = 0;
|
|
if (i == 0)
|
|
radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv;
|
|
else
|
|
radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv;
|
|
|
|
}
|
|
/* Add ttm page pool to debugfs */
|
|
sprintf(radeon_mem_types_names[i], "ttm_page_pool");
|
|
radeon_mem_types_list[i].name = radeon_mem_types_names[i];
|
|
radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs;
|
|
radeon_mem_types_list[i].driver_features = 0;
|
|
radeon_mem_types_list[i++].data = NULL;
|
|
#ifdef CONFIG_SWIOTLB
|
|
if (swiotlb_nr_tbl()) {
|
|
sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool");
|
|
radeon_mem_types_list[i].name = radeon_mem_types_names[i];
|
|
radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs;
|
|
radeon_mem_types_list[i].driver_features = 0;
|
|
radeon_mem_types_list[i++].data = NULL;
|
|
}
|
|
#endif
|
|
return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i);
|
|
|
|
#endif
|
|
return 0;
|
|
}
|