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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7ab3f021bb
If register value is updating, reset timeout counter. It improves robustness of SOC15_WAIT_ON_RREG. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
95 lines
3.8 KiB
C
95 lines
3.8 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SOC15_COMMON_H__
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#define __SOC15_COMMON_H__
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/* Register Access Macros */
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#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
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#define WREG32_FIELD15(ip, idx, reg, field, val) \
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WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
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(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
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& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
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#define RREG32_SOC15(ip, inst, reg) \
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RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
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#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
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RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
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#define WREG32_SOC15(ip, inst, reg, value) \
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WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
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#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
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WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
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#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
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WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
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#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \
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do { \
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uint32_t old_ = 0; \
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uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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uint32_t loop = adev->usec_timeout; \
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while ((tmp_ & (mask)) != (expected_value)) { \
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if (old_ != tmp_) { \
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loop = adev->usec_timeout; \
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old_ = tmp_; \
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} else \
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udelay(1); \
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tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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loop--; \
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if (!loop) { \
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DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
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inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
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ret = -ETIMEDOUT; \
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break; \
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} \
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} \
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} while (0)
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#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
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({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__MASK_EN_MASK | \
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((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); })
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#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
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do { \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
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((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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} while (0)
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#endif
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