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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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133e6c78c4
The plan for the HiHope RZ/G2N board is to enable pciec0 by default, and use pciec1 physical interface for SATA (as SATA and PCIE1 share the same physical interface), therefore move pciec1 enabling away from hihope-rzg2-ex. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Link: https://lore.kernel.org/r/1570178133-21532-8-git-send-email-fabrizio.castro@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
131 lines
2.1 KiB
Plaintext
131 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the RZ/G2[MN] HiHope sub board common parts
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*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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/ {
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aliases {
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ethernet0 = &avb;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm0 0 50000>;
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brightness-levels = <0 2 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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};
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};
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&avb {
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pinctrl-0 = <&avb_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-txid";
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status = "okay";
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio2>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
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};
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};
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&can0 {
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pinctrl-0 = <&can0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&can1 {
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pinctrl-0 = <&can1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&gpio1 {
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/*
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* When GP1_20 is LOW LVDS0 is connected to the LVDS connector
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* When GP1_20 is HIGH LVDS0 is connected to the LT8918L
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*/
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lvds-connector-en-gpio {
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gpio-hog;
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gpios = <20 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "lvds-connector-en-gpio";
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};
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};
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&lvds0 {
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/*
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* Please include the LVDS panel .dtsi file and uncomment the below line
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* to enable LVDS panel connected to RZ/G2[MN] boards.
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*/
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/* status = "okay"; */
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ports {
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port@1 {
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lvds_connector: endpoint {
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};
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};
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};
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};
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&pciec0 {
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status = "okay";
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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avb_pins: avb {
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mux {
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groups = "avb_link", "avb_mdio", "avb_mii";
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function = "avb";
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};
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pins_mdio {
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groups = "avb_mdio";
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drive-strength = <24>;
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};
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pins_mii_tx {
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pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
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"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
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drive-strength = <12>;
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};
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};
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can0_pins: can0 {
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groups = "can0_data_a";
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function = "can0";
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};
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can1_pins: can1 {
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groups = "can1_data";
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function = "can1";
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};
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pwm0_pins: pwm0 {
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groups = "pwm0";
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function = "pwm0";
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};
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};
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&pwm0 {
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pinctrl-0 = <&pwm0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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