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Using 64k pages on 64-bit PowerPC systems makes life difficult for emulators that are trying to emulate an ISA, such as x86, which use a smaller page size, since the emulator can no longer use the MMU and the normal system calls for controlling page protections. Of course, the emulator can emulate the MMU by checking and possibly remapping the address for each memory access in software, but that is pretty slow. This provides a facility for such programs to control the access permissions on individual 4k sub-pages of 64k pages. The idea is that the emulator supplies an array of protection masks to apply to a specified range of virtual addresses. These masks are applied at the level where hardware PTEs are inserted into the hardware page table based on the Linux PTEs, so the Linux PTEs are not affected. Note that this new mechanism does not allow any access that would otherwise be prohibited; it can only prohibit accesses that would otherwise be allowed. This new facility is only available on 64-bit PowerPC and only when the kernel is configured for 64k pages. The masks are supplied using a new subpage_prot system call, which takes a starting virtual address and length, and a pointer to an array of protection masks in memory. The array has a 32-bit word per 64k page to be protected; each 32-bit word consists of 16 2-bit fields, for which 0 allows any access (that is otherwise allowed), 1 prevents write accesses, and 2 or 3 prevent any access. Implicit in this is that the regions of the address space that are protected are switched to use 4k hardware pages rather than 64k hardware pages (on machines with hardware 64k page support). In fact the whole process is switched to use 4k hardware pages when the subpage_prot system call is used, but this could be improved in future to switch only the affected segments. The subpage protection bits are stored in a 3 level tree akin to the page table tree. The top level of this tree is stored in a structure that is appended to the top level of the page table tree, i.e., the pgd array. Since it will often only be 32-bit addresses (below 4GB) that are protected, the pointers to the first four bottom level pages are also stored in this structure (each bottom level page contains the protection bits for 1GB of address space), so the protection bits for addresses below 4GB can be accessed with one fewer loads than those for higher addresses. Signed-off-by: Paul Mackerras <paulus@samba.org>
141 lines
5.2 KiB
C
141 lines
5.2 KiB
C
#ifndef _ASM_POWERPC_PGTABLE_64K_H
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#define _ASM_POWERPC_PGTABLE_64K_H
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#include <asm-generic/pgtable-nopud.h>
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#define PTE_INDEX_SIZE 12
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#define PMD_INDEX_SIZE 12
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#define PUD_INDEX_SIZE 0
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#define PGD_INDEX_SIZE 4
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#ifndef __ASSEMBLY__
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#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
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#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
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#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
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#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
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#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
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#ifdef CONFIG_PPC_SUBPAGE_PROT
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/*
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* For the sub-page protection option, we extend the PGD with one of
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* these. Basically we have a 3-level tree, with the top level being
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* the protptrs array. To optimize speed and memory consumption when
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* only addresses < 4GB are being protected, pointers to the first
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* four pages of sub-page protection words are stored in the low_prot
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* array.
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* Each page of sub-page protection words protects 1GB (4 bytes
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* protects 64k). For the 3-level tree, each page of pointers then
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* protects 8TB.
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*/
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struct subpage_prot_table {
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unsigned long maxaddr; /* only addresses < this are protected */
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unsigned int **protptrs[2];
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unsigned int *low_prot[4];
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};
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#undef PGD_TABLE_SIZE
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#define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \
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sizeof(struct subpage_prot_table))
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#define SBP_L1_BITS (PAGE_SHIFT - 2)
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#define SBP_L2_BITS (PAGE_SHIFT - 3)
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#define SBP_L1_COUNT (1 << SBP_L1_BITS)
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#define SBP_L2_COUNT (1 << SBP_L2_BITS)
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#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
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#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
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extern void subpage_prot_free(pgd_t *pgd);
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static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
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{
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return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD);
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}
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#endif /* CONFIG_PPC_SUBPAGE_PROT */
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#endif /* __ASSEMBLY__ */
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/* With 4k base page size, hugepage PTEs go at the PMD level */
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#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
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/* PMD_SHIFT determines what a second-level page table entry can map */
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#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* Additional PTE bits (don't change without checking asm in hash_low.S) */
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#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
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#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
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#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
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#define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */
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/* Note the full page bits must be in the same location as for normal
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* 4k pages as the same asssembly will be used to insert 64K pages
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* wether the kernel has CONFIG_PPC_64K_PAGES or not
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*/
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#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
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#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
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/* PTE flags to conserve for HPTE identification */
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#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\
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_PAGE_COMBO)
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/* Shift to put page number into pte.
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*
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* That gives us a max RPN of 34 bits, which means a max of 50 bits
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* of addressable physical space, or 46 bits for the special 4k PFNs.
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*/
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#define PTE_RPN_SHIFT (30)
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#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
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#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
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/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
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* pgprot changes
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*/
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#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
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_PAGE_ACCESSED)
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/* Bits to mask out from a PMD to get to the PTE page */
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#define PMD_MASKED_BITS 0x1ff
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/* Bits to mask out from a PGD/PUD to get to the PMD page */
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#define PUD_MASKED_BITS 0x1ff
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/* Manipulate "rpte" values */
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#define __real_pte(e,p) ((real_pte_t) { \
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(e), pte_val(*((p) + PTRS_PER_PTE)) })
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#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
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(((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
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#define __rpte_to_pte(r) ((r).pte)
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#define __rpte_sub_valid(rpte, index) \
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(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
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/* Trick: we set __end to va + 64k, which happens works for
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* a 16M page as well as we want only one iteration
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*/
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#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
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do { \
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unsigned long __end = va + PAGE_SIZE; \
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unsigned __split = (psize == MMU_PAGE_4K || \
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psize == MMU_PAGE_64K_AP); \
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shift = mmu_psize_defs[psize].shift; \
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for (index = 0; va < __end; index++, va += (1 << shift)) { \
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if (!__split || __rpte_sub_valid(rpte, index)) do { \
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#define pte_iterate_hashed_end() } while(0); } } while(0)
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#define pte_pagesize_index(mm, addr, pte) \
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(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
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__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
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#endif /* _ASM_POWERPC_PGTABLE_64K_H */
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