mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 05:20:25 +07:00
e6e2df69c8
Rework portal mapping for PPC and ARM. The PPC devices require a cacheable coherent mapping while ARM will work with a non-cachable/write combine mapping. This also eliminates the need for manual cache flushes on ARM. This also fixes the code so sparse checking is clean. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
79 lines
3.1 KiB
C
79 lines
3.1 KiB
C
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are met:
|
|
* * Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* * Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
* * Neither the name of Freescale Semiconductor nor the
|
|
* names of its contributors may be used to endorse or promote products
|
|
* derived from this software without specific prior written permission.
|
|
*
|
|
* ALTERNATIVELY, this software may be distributed under the terms of the
|
|
* GNU General Public License ("GPL") as published by the Free Software
|
|
* Foundation, either version 2 of that License or (at your option) any
|
|
* later version.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
|
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
|
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
|
|
|
#include "dpaa_sys.h"
|
|
|
|
#include <soc/fsl/bman.h>
|
|
|
|
/* Portal processing (interrupt) sources */
|
|
#define BM_PIRQ_RCRI 0x00000002 /* RCR Ring (below threshold) */
|
|
|
|
/* Revision info (for errata and feature handling) */
|
|
#define BMAN_REV10 0x0100
|
|
#define BMAN_REV20 0x0200
|
|
#define BMAN_REV21 0x0201
|
|
extern u16 bman_ip_rev; /* 0 if uninitialised, otherwise BMAN_REVx */
|
|
|
|
extern struct gen_pool *bm_bpalloc;
|
|
|
|
struct bm_portal_config {
|
|
/* Portal addresses */
|
|
void *addr_virt_ce;
|
|
void __iomem *addr_virt_ci;
|
|
/* Allow these to be joined in lists */
|
|
struct list_head list;
|
|
struct device *dev;
|
|
/* User-visible portal configuration settings */
|
|
/* portal is affined to this cpu */
|
|
int cpu;
|
|
/* portal interrupt line */
|
|
int irq;
|
|
};
|
|
|
|
struct bman_portal *bman_create_affine_portal(
|
|
const struct bm_portal_config *config);
|
|
/*
|
|
* The below bman_p_***() variant might be called in a situation that the cpu
|
|
* which the portal affine to is not online yet.
|
|
* @bman_portal specifies which portal the API will use.
|
|
*/
|
|
int bman_p_irqsource_add(struct bman_portal *p, u32 bits);
|
|
|
|
/*
|
|
* Used by all portal interrupt registers except 'inhibit'
|
|
* This mask contains all the "irqsource" bits visible to API users
|
|
*/
|
|
#define BM_PIRQ_VISIBLE BM_PIRQ_RCRI
|
|
|
|
const struct bm_portal_config *
|
|
bman_get_bm_portal_config(const struct bman_portal *portal);
|