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49a06cae6e
On the Allwinner R40 SoC, the "GMAC clock" register is in the CCU address space. Using a standard syscon to access it provides no coordination with the CCU driver for register access. Neither does it prevent this and other drivers from accessing other, maybe critical, clock control registers. On other SoCs, the register is in the "system control" address space, which might also contain controls for mapping SRAM to devices or the CPU. This hardware has the same issues. Instead, for these types of setups, we let the device containing the control register create a regmap tied to it. We can then get the device from the existing syscon phandle, and retrieve the regmap with dev_get_regmap(). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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3com | ||
8390 | ||
adaptec | ||
aeroflex | ||
agere | ||
alacritech | ||
allwinner | ||
alteon | ||
altera | ||
amazon | ||
amd | ||
apm | ||
apple | ||
aquantia | ||
arc | ||
atheros | ||
aurora | ||
broadcom | ||
brocade | ||
cadence | ||
calxeda | ||
cavium | ||
chelsio | ||
cirrus | ||
cisco | ||
cortina | ||
davicom | ||
dec | ||
dlink | ||
emulex | ||
ezchip | ||
faraday | ||
freescale | ||
fujitsu | ||
hisilicon | ||
hp | ||
huawei | ||
i825xx | ||
ibm | ||
intel | ||
marvell | ||
mediatek | ||
mellanox | ||
micrel | ||
microchip | ||
moxa | ||
myricom | ||
natsemi | ||
neterion | ||
netronome | ||
ni | ||
nuvoton | ||
nvidia | ||
nxp | ||
oki-semi | ||
packetengines | ||
pasemi | ||
qlogic | ||
qualcomm | ||
rdc | ||
realtek | ||
renesas | ||
rocker | ||
samsung | ||
seeq | ||
sfc | ||
sgi | ||
silan | ||
sis | ||
smsc | ||
socionext | ||
stmicro | ||
sun | ||
synopsys | ||
tehuti | ||
ti | ||
toshiba | ||
tundra | ||
via | ||
wiznet | ||
xilinx | ||
xircom | ||
xscale | ||
dnet.c | ||
dnet.h | ||
ec_bhf.c | ||
ethoc.c | ||
fealnx.c | ||
jme.c | ||
jme.h | ||
Kconfig | ||
korina.c | ||
lantiq_etop.c | ||
Makefile | ||
netx-eth.c |