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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
499ccb27a8
Standarize and document the FPGA nodes used on Freescale QorIQ reference boards. There are different kinds of FPGAs used on the boards, but only two are currently standard: "pixis", "ngpixis", and "qixis". Although there are minor differences among the boards that have one kind of FPGA, most of the functionality is the same, so it makes sense to create common compatibility strings. We also need to update the P1022DS platform file, because the compatible string for its PIXIS node has changed. This means that older kernels are not compatible with newer device trees. This is not a real problem, however, since that particular function doesn't work anyway. When the DIU is active, the PIXIS is in "indirect mode", and so cannot be accessed as a memory-mapped device. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
658 lines
14 KiB
Plaintext
658 lines
14 KiB
Plaintext
/*
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* P1022 DS 36Bit Physical Address Map Device Tree Source
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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/ {
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model = "fsl,P1022";
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compatible = "fsl,P1022DS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,P1022@0 {
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device_type = "cpu";
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reg = <0x0>;
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next-level-cache = <&L2>;
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};
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PowerPC,P1022@1 {
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device_type = "cpu";
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reg = <0x1>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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};
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localbus@fffe05000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
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reg = <0 0xffe05000 0 0x1000>;
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interrupts = <19 2 0 0>;
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ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
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0x1 0x0 0xf 0xe0000000 0x08000000
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0x2 0x0 0x0 0xffa00000 0x00040000
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0x3 0x0 0xf 0xffdf0000 0x00008000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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reg = <0x0 0x03000000>;
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label = "ramdisk-nor";
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read-only;
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};
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partition@3000000 {
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reg = <0x03000000 0x00e00000>;
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label = "diagnostic-nor";
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read-only;
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};
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partition@3e00000 {
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reg = <0x03e00000 0x00200000>;
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label = "dink-nor";
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read-only;
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};
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partition@4000000 {
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reg = <0x04000000 0x00400000>;
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label = "kernel-nor";
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read-only;
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};
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partition@4400000 {
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reg = <0x04400000 0x03b00000>;
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label = "jffs2-nor";
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};
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partition@7f00000 {
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reg = <0x07f00000 0x00080000>;
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label = "dtb-nor";
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read-only;
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};
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partition@7f80000 {
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reg = <0x07f80000 0x00080000>;
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label = "u-boot-nor";
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read-only;
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};
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};
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nand@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,elbc-fcm-nand";
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reg = <0x2 0x0 0x40000>;
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partition@0 {
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reg = <0x0 0x02000000>;
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label = "u-boot-nand";
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read-only;
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};
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partition@2000000 {
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reg = <0x02000000 0x10000000>;
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label = "jffs2-nand";
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};
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partition@12000000 {
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reg = <0x12000000 0x10000000>;
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label = "ramdisk-nand";
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read-only;
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};
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partition@22000000 {
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reg = <0x22000000 0x04000000>;
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label = "kernel-nand";
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};
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partition@26000000 {
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reg = <0x26000000 0x01000000>;
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label = "dtb-nand";
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read-only;
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};
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partition@27000000 {
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reg = <0x27000000 0x19000000>;
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label = "reserved-nand";
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};
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};
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board-control@3,0 {
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compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
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reg = <3 0 0x30>;
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interrupt-parent = <&mpic>;
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/*
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* IRQ8 is generated if the "EVENT" switch is pressed
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* and PX_CTL[EVESEL] is set to 00.
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*/
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interrupts = <8 8 0 0>;
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};
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};
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soc@fffe00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,p1022-immr", "simple-bus";
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ranges = <0x0 0xf 0xffe00000 0x100000>;
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bus-frequency = <0>; // Filled out by uboot.
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,p1022-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <16 2 0 0>;
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};
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memory-controller@2000 {
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compatible = "fsl,p1022-memory-controller";
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reg = <0x2000 0x1000>;
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interrupts = <16 2 0 0>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2 0 0>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2 0 0>;
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dfsrr;
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wm8776:codec@1a {
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compatible = "wlf,wm8776";
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reg = <0x1a>;
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/*
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* clock-frequency will be set by U-Boot if
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* the clock is enabled.
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*/
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2 0 0>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2 0 0>;
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};
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spi@7000 {
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cell-index = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,espi";
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reg = <0x7000 0x1000>;
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interrupts = <59 0x2 0 0>;
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espi,num-ss-bits = <4>;
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mode = "cpu";
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fsl_m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,espi-flash";
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reg = <0>;
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linux,modalias = "fsl_m25p80";
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spi-max-frequency = <40000000>; /* input clock */
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partition@0 {
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label = "u-boot-spi";
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reg = <0x00000000 0x00100000>;
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read-only;
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};
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partition@100000 {
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label = "kernel-spi";
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reg = <0x00100000 0x00500000>;
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read-only;
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};
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partition@600000 {
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label = "dtb-spi";
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reg = <0x00600000 0x00100000>;
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read-only;
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};
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partition@700000 {
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label = "file system-spi";
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reg = <0x00700000 0x00900000>;
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};
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};
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};
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ssi@15000 {
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compatible = "fsl,mpc8610-ssi";
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cell-index = <0>;
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reg = <0x15000 0x100>;
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interrupts = <75 2 0 0>;
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fsl,mode = "i2s-slave";
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codec-handle = <&wm8776>;
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fsl,playback-dma = <&dma00>;
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fsl,capture-dma = <&dma01>;
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fsl,fifo-depth = <15>;
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fsl,ssi-asynchronous;
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};
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dma@c300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,eloplus-dma";
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reg = <0xc300 0x4>;
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ranges = <0x0 0xc100 0x200>;
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cell-index = <1>;
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dma00: dma-channel@0 {
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compatible = "fsl,ssi-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupts = <76 2 0 0>;
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};
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dma01: dma-channel@80 {
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compatible = "fsl,ssi-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupts = <77 2 0 0>;
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};
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dma-channel@100 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupts = <78 2 0 0>;
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};
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dma-channel@180 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupts = <79 2 0 0>;
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};
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};
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gpio: gpio-controller@f000 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8572-gpio";
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reg = <0xf000 0x100>;
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interrupts = <47 0x2 0 0>;
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gpio-controller;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,p1022-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x40000>; // L2, 256K
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interrupts = <16 2 0 0>;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupts = <20 2 0 0>;
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};
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dma-channel@80 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupts = <21 2 0 0>;
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};
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dma-channel@100 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupts = <22 2 0 0>;
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};
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dma-channel@180 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupts = <23 2 0 0>;
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};
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};
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usb@22000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-usb2-dr";
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reg = <0x22000 0x1000>;
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interrupts = <28 0x2 0 0>;
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phy_type = "ulpi";
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};
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mdio@24000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,etsec2-mdio";
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reg = <0x24000 0x1000 0xb0030 0x4>;
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phy0: ethernet-phy@0 {
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interrupts = <3 1 0 0>;
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reg = <0x1>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <9 1 0 0>;
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reg = <0x2>;
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};
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};
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mdio@25000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,etsec2-mdio";
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reg = <0x25000 0x1000 0xb1030 0x4>;
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};
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enet0: ethernet@B0000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "fsl,etsec2";
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fsl,num_rx_queues = <0x8>;
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fsl,num_tx_queues = <0x8>;
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fsl,magic-packet;
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fsl,wake-on-filer;
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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queue-group@0{
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xB0000 0x1000>;
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interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
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};
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queue-group@1{
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xB4000 0x1000>;
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interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
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};
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};
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enet1: ethernet@B1000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "fsl,etsec2";
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fsl,num_rx_queues = <0x8>;
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fsl,num_tx_queues = <0x8>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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queue-group@0{
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xB1000 0x1000>;
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interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
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};
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queue-group@1{
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xB5000 0x1000>;
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interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
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};
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};
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sdhci@2e000 {
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compatible = "fsl,p1022-esdhc", "fsl,esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <72 0x2 0 0>;
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fsl,sdhci-auto-cmd12;
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/* Filled in by U-Boot */
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clock-frequency = <0>;
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};
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crypto@30000 {
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compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
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"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
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"fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <45 2 0 0 58 2 0 0>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x97c>;
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fsl,descriptor-types-mask = <0x3a30abf>;
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};
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sata@18000 {
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compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
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reg = <0x18000 0x1000>;
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cell-index = <1>;
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interrupts = <74 0x2 0 0>;
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};
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sata@19000 {
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compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
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reg = <0x19000 0x1000>;
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cell-index = <2>;
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interrupts = <41 0x2 0 0>;
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};
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power@e0070{
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compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
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reg = <0xe0070 0x20>;
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};
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display@10000 {
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compatible = "fsl,diu", "fsl,p1022-diu";
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reg = <0x10000 1000>;
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interrupts = <64 2 0 0>;
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};
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timer@41100 {
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compatible = "fsl,mpic-global-timer";
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reg = <0x41100 0x100 0x41300 4>;
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interrupts = <0 0 3 0
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1 0 3 0
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2 0 3 0
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3 0 3 0>;
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};
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timer@42100 {
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compatible = "fsl,mpic-global-timer";
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reg = <0x42100 0x100 0x42300 4>;
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interrupts = <4 0 3 0
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5 0 3 0
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6 0 3 0
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7 0 3 0>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <4>;
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reg = <0x40000 0x40000>;
|
|
compatible = "fsl,mpic";
|
|
device_type = "open-pic";
|
|
};
|
|
|
|
msi@41600 {
|
|
compatible = "fsl,p1022-msi", "fsl,mpic-msi";
|
|
reg = <0x41600 0x80>;
|
|
msi-available-ranges = <0 0x100>;
|
|
interrupts = <
|
|
0xe0 0 0 0
|
|
0xe1 0 0 0
|
|
0xe2 0 0 0
|
|
0xe3 0 0 0
|
|
0xe4 0 0 0
|
|
0xe5 0 0 0
|
|
0xe6 0 0 0
|
|
0xe7 0 0 0>;
|
|
};
|
|
|
|
global-utilities@e0000 { //global utilities block
|
|
compatible = "fsl,p1022-guts";
|
|
reg = <0xe0000 0x1000>;
|
|
fsl,has-rstcr;
|
|
};
|
|
};
|
|
|
|
pci0: pcie@fffe09000 {
|
|
compatible = "fsl,p1022-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xf 0xffe09000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
|
|
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
|
|
clock-frequency = <33333333>;
|
|
interrupts = <16 2 0 0>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0 0 1 &mpic 4 1
|
|
0000 0 0 2 &mpic 5 1
|
|
0000 0 0 3 &mpic 6 1
|
|
0000 0 0 4 &mpic 7 1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xe0000000
|
|
0x2000000 0x0 0xe0000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x100000>;
|
|
};
|
|
};
|
|
|
|
pci1: pcie@fffe0a000 {
|
|
compatible = "fsl,p1022-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xf 0xffe0a000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
|
|
0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
|
|
clock-frequency = <33333333>;
|
|
interrupts = <16 2 0 0>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0 0 1 &mpic 0 1
|
|
0000 0 0 2 &mpic 1 1
|
|
0000 0 0 3 &mpic 2 1
|
|
0000 0 0 4 &mpic 3 1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xe0000000
|
|
0x2000000 0x0 0xe0000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x100000>;
|
|
};
|
|
};
|
|
|
|
|
|
pci2: pcie@fffe0b000 {
|
|
compatible = "fsl,p1022-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xf 0xffe0b000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
|
|
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
|
|
clock-frequency = <33333333>;
|
|
interrupts = <16 2 0 0>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0 0 1 &mpic 8 1
|
|
0000 0 0 2 &mpic 9 1
|
|
0000 0 0 3 &mpic 10 1
|
|
0000 0 0 4 &mpic 11 1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xe0000000
|
|
0x2000000 0x0 0xe0000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x100000>;
|
|
};
|
|
};
|
|
};
|