mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 03:16:39 +07:00
57e5568fda
Enable IRQ on hotplug and add an interrupt handler to handle it. This allows hotplug to work: ata5: exception Emask 0x10 SAct 0x0 SErr 0x70000 action 0xe frozen ata5: SError: { PHYRdyChg PHYInt CommWake } ata5: hard resetting link ata5: SATA link up 1.5 Gbps (SStatus 113 SControl 310) ata5.00: LPM support broken, forcing max_power ata5.00: ATA-7: WDC WD800JD-75MSA3, 10.01E04, max UDMA/133 ata5.00: 156250000 sectors, multi 0: LBA48 NCQ (depth 0/32) ata5.00: LPM support broken, forcing max_power ata5.00: configured for UDMA/133 ata5: EH complete scsi 4:0:0:0: Direct-Access ATA WDC WD800JD-75MS 1E04 PQ: 0 ANSI: 5 sd 4:0:0:0: [sdb] 156250000 512-byte logical blocks: (80.0 GB/74.5 GiB) sd 4:0:0:0: [sdb] Write Protect is off sd 4:0:0:0: [sdb] Mode Sense: 00 3a 00 00 sd 4:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sd 4:0:0:0: Attached scsi generic sg1 type 0 sd 4:0:0:0: [sdb] Attached SCSI disk And also hot unplug: ata5: exception Emask 0x10 SAct 0x0 SErr 0x1b0000 action 0xe frozen ata5: SError: { PHYRdyChg PHYInt 10B8B Dispar } ata5: hard resetting link ata5: SATA link down (SStatus 0 SControl 310) ata5: hard resetting link ata5: SATA link down (SStatus 0 SControl 310) ata5: hard resetting link ata5: SATA link down (SStatus 0 SControl 310) ata5.00: disabled ata5: EH complete ata5.00: detaching (SCSI 4:0:0:0) sd 4:0:0:0: [sdb] Synchronizing SCSI cache sd 4:0:0:0: [sdb] Synchronize Cache(10) failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK sd 4:0:0:0: [sdb] Stopping disk sd 4:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Tejun Heo <tj@kernel.org>
773 lines
21 KiB
C
773 lines
21 KiB
C
/*
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* sata_via.c - VIA Serial ATA controllers
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*
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* Maintained by: Tejun Heo <tj@kernel.org>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003-2004 Red Hat, Inc. All rights reserved.
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* Copyright 2003-2004 Jeff Garzik
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available under NDA.
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*
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*
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi.h>
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#include <scsi/scsi_cmnd.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "sata_via"
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#define DRV_VERSION "2.6"
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/*
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* vt8251 is different from other sata controllers of VIA. It has two
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* channels, each channel has both Master and Slave slot.
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*/
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enum board_ids_enum {
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vt6420,
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vt6421,
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vt8251,
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};
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enum {
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SATA_CHAN_ENAB = 0x40, /* SATA channel enable */
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SATA_INT_GATE = 0x41, /* SATA interrupt gating */
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SATA_NATIVE_MODE = 0x42, /* Native mode enable */
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SVIA_MISC_3 = 0x46, /* Miscellaneous Control III */
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PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */
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PATA_PIO_TIMING = 0xAB, /* PATA timing register */
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PORT0 = (1 << 1),
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PORT1 = (1 << 0),
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ALL_PORTS = PORT0 | PORT1,
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NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),
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SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
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SATA_HOTPLUG = (1 << 5), /* enable IRQ on hotplug */
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};
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struct svia_priv {
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bool wd_workaround;
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};
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static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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#ifdef CONFIG_PM_SLEEP
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static int svia_pci_device_resume(struct pci_dev *pdev);
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#endif
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static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
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static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
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static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val);
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static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val);
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static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf);
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static void svia_noop_freeze(struct ata_port *ap);
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static int vt6420_prereset(struct ata_link *link, unsigned long deadline);
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static void vt6420_bmdma_start(struct ata_queued_cmd *qc);
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static int vt6421_pata_cable_detect(struct ata_port *ap);
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static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
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static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);
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static void vt6421_error_handler(struct ata_port *ap);
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static const struct pci_device_id svia_pci_tbl[] = {
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{ PCI_VDEVICE(VIA, 0x5337), vt6420 },
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{ PCI_VDEVICE(VIA, 0x0591), vt6420 }, /* 2 sata chnls (Master) */
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{ PCI_VDEVICE(VIA, 0x3149), vt6420 }, /* 2 sata chnls (Master) */
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{ PCI_VDEVICE(VIA, 0x3249), vt6421 }, /* 2 sata chnls, 1 pata chnl */
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{ PCI_VDEVICE(VIA, 0x5372), vt6420 },
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{ PCI_VDEVICE(VIA, 0x7372), vt6420 },
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{ PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */
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{ PCI_VDEVICE(VIA, 0x9000), vt8251 },
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{ } /* terminate list */
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};
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static struct pci_driver svia_pci_driver = {
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.name = DRV_NAME,
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.id_table = svia_pci_tbl,
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.probe = svia_init_one,
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#ifdef CONFIG_PM_SLEEP
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.suspend = ata_pci_device_suspend,
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.resume = svia_pci_device_resume,
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#endif
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.remove = ata_pci_remove_one,
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};
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static struct scsi_host_template svia_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations svia_base_ops = {
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.inherits = &ata_bmdma_port_ops,
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.sff_tf_load = svia_tf_load,
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};
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static struct ata_port_operations vt6420_sata_ops = {
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.inherits = &svia_base_ops,
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.freeze = svia_noop_freeze,
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.prereset = vt6420_prereset,
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.bmdma_start = vt6420_bmdma_start,
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};
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static struct ata_port_operations vt6421_pata_ops = {
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.inherits = &svia_base_ops,
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.cable_detect = vt6421_pata_cable_detect,
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.set_piomode = vt6421_set_pio_mode,
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.set_dmamode = vt6421_set_dma_mode,
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};
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static struct ata_port_operations vt6421_sata_ops = {
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.inherits = &svia_base_ops,
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.scr_read = svia_scr_read,
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.scr_write = svia_scr_write,
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.error_handler = vt6421_error_handler,
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};
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static struct ata_port_operations vt8251_ops = {
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.inherits = &svia_base_ops,
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.hardreset = sata_std_hardreset,
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.scr_read = vt8251_scr_read,
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.scr_write = vt8251_scr_write,
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};
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static const struct ata_port_info vt6420_port_info = {
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.flags = ATA_FLAG_SATA,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA6,
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.port_ops = &vt6420_sata_ops,
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};
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static struct ata_port_info vt6421_sport_info = {
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.flags = ATA_FLAG_SATA,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA6,
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.port_ops = &vt6421_sata_ops,
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};
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static struct ata_port_info vt6421_pport_info = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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/* No MWDMA */
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.udma_mask = ATA_UDMA6,
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.port_ops = &vt6421_pata_ops,
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};
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static struct ata_port_info vt8251_port_info = {
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.flags = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA6,
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.port_ops = &vt8251_ops,
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};
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MODULE_AUTHOR("Jeff Garzik");
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MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
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{
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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*val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg));
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return 0;
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}
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static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
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{
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg));
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return 0;
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}
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static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
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{
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static const u8 ipm_tbl[] = { 1, 2, 6, 0 };
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struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
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int slot = 2 * link->ap->port_no + link->pmp;
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u32 v = 0;
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u8 raw;
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switch (scr) {
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case SCR_STATUS:
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pci_read_config_byte(pdev, 0xA0 + slot, &raw);
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/* read the DET field, bit0 and 1 of the config byte */
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v |= raw & 0x03;
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/* read the SPD field, bit4 of the configure byte */
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if (raw & (1 << 4))
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v |= 0x02 << 4;
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else
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v |= 0x01 << 4;
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/* read the IPM field, bit2 and 3 of the config byte */
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v |= ipm_tbl[(raw >> 2) & 0x3];
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break;
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case SCR_ERROR:
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/* devices other than 5287 uses 0xA8 as base */
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WARN_ON(pdev->device != 0x5287);
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pci_read_config_dword(pdev, 0xB0 + slot * 4, &v);
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break;
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case SCR_CONTROL:
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pci_read_config_byte(pdev, 0xA4 + slot, &raw);
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/* read the DET field, bit0 and bit1 */
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v |= ((raw & 0x02) << 1) | (raw & 0x01);
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/* read the IPM field, bit2 and bit3 */
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v |= ((raw >> 2) & 0x03) << 8;
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break;
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default:
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return -EINVAL;
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}
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*val = v;
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return 0;
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}
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static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val)
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{
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struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
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int slot = 2 * link->ap->port_no + link->pmp;
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u32 v = 0;
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switch (scr) {
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case SCR_ERROR:
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/* devices other than 5287 uses 0xA8 as base */
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WARN_ON(pdev->device != 0x5287);
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pci_write_config_dword(pdev, 0xB0 + slot * 4, val);
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return 0;
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case SCR_CONTROL:
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/* set the DET field */
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v |= ((val & 0x4) >> 1) | (val & 0x1);
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/* set the IPM field */
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v |= ((val >> 8) & 0x3) << 2;
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pci_write_config_byte(pdev, 0xA4 + slot, v);
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return 0;
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default:
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return -EINVAL;
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}
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}
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/**
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* svia_tf_load - send taskfile registers to host controller
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* @ap: Port to which output is sent
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* @tf: ATA taskfile register set
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*
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* Outputs ATA taskfile to standard ATA host controller.
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*
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* This is to fix the internal bug of via chipsets, which will
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* reset the device register after changing the IEN bit on ctl
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* register.
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*/
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static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_taskfile ttf;
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if (tf->ctl != ap->last_ctl) {
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ttf = *tf;
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ttf.flags |= ATA_TFLAG_DEVICE;
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tf = &ttf;
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}
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ata_sff_tf_load(ap, tf);
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}
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static void svia_noop_freeze(struct ata_port *ap)
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{
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/* Some VIA controllers choke if ATA_NIEN is manipulated in
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* certain way. Leave it alone and just clear pending IRQ.
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*/
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ap->ops->sff_check_status(ap);
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ata_bmdma_irq_clear(ap);
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}
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/**
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* vt6420_prereset - prereset for vt6420
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* @link: target ATA link
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* @deadline: deadline jiffies for the operation
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*
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* SCR registers on vt6420 are pieces of shit and may hang the
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* whole machine completely if accessed with the wrong timing.
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* To avoid such catastrophe, vt6420 doesn't provide generic SCR
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* access operations, but uses SStatus and SControl only during
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* boot probing in controlled way.
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*
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* As the old (pre EH update) probing code is proven to work, we
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* strictly follow the access pattern.
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*
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* LOCKING:
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* Kernel thread context (may sleep)
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*
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* RETURNS:
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* 0 on success, -errno otherwise.
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*/
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static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct ata_eh_context *ehc = &ap->link.eh_context;
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unsigned long timeout = jiffies + (HZ * 5);
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u32 sstatus, scontrol;
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int online;
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/* don't do any SCR stuff if we're not loading */
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if (!(ap->pflags & ATA_PFLAG_LOADING))
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goto skip_scr;
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/* Resume phy. This is the old SATA resume sequence */
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svia_scr_write(link, SCR_CONTROL, 0x300);
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svia_scr_read(link, SCR_CONTROL, &scontrol); /* flush */
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/* wait for phy to become ready, if necessary */
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do {
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ata_msleep(link->ap, 200);
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svia_scr_read(link, SCR_STATUS, &sstatus);
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if ((sstatus & 0xf) != 1)
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break;
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} while (time_before(jiffies, timeout));
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/* open code sata_print_link_status() */
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svia_scr_read(link, SCR_STATUS, &sstatus);
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svia_scr_read(link, SCR_CONTROL, &scontrol);
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online = (sstatus & 0xf) == 0x3;
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ata_port_info(ap,
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"SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
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online ? "up" : "down", sstatus, scontrol);
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/* SStatus is read one more time */
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svia_scr_read(link, SCR_STATUS, &sstatus);
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if (!online) {
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/* tell EH to bail */
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ehc->i.action &= ~ATA_EH_RESET;
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return 0;
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}
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skip_scr:
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/* wait for !BSY */
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ata_sff_wait_ready(link, deadline);
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return 0;
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}
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static void vt6420_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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if ((qc->tf.command == ATA_CMD_PACKET) &&
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(qc->scsicmd->sc_data_direction == DMA_TO_DEVICE)) {
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/* Prevents corruption on some ATAPI burners */
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ata_sff_pause(ap);
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}
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ata_bmdma_start(qc);
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}
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static int vt6421_pata_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 tmp;
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pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
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if (tmp & 0x10)
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
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pci_write_config_byte(pdev, PATA_PIO_TIMING - adev->devno,
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pio_bits[adev->pio_mode - XFER_PIO_0]);
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}
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static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
|
|
pci_write_config_byte(pdev, PATA_UDMA_TIMING - adev->devno,
|
|
udma_bits[adev->dma_mode - XFER_UDMA_0]);
|
|
}
|
|
|
|
static const unsigned int svia_bar_sizes[] = {
|
|
8, 4, 8, 4, 16, 256
|
|
};
|
|
|
|
static const unsigned int vt6421_bar_sizes[] = {
|
|
16, 16, 16, 16, 32, 128
|
|
};
|
|
|
|
static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port)
|
|
{
|
|
return addr + (port * 128);
|
|
}
|
|
|
|
static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port)
|
|
{
|
|
return addr + (port * 64);
|
|
}
|
|
|
|
static void vt6421_init_addrs(struct ata_port *ap)
|
|
{
|
|
void __iomem * const * iomap = ap->host->iomap;
|
|
void __iomem *reg_addr = iomap[ap->port_no];
|
|
void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8);
|
|
struct ata_ioports *ioaddr = &ap->ioaddr;
|
|
|
|
ioaddr->cmd_addr = reg_addr;
|
|
ioaddr->altstatus_addr =
|
|
ioaddr->ctl_addr = (void __iomem *)
|
|
((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
|
|
ioaddr->bmdma_addr = bmdma_addr;
|
|
ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);
|
|
|
|
ata_sff_std_ports(ioaddr);
|
|
|
|
ata_port_pbar_desc(ap, ap->port_no, -1, "port");
|
|
ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma");
|
|
}
|
|
|
|
static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
|
|
{
|
|
const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
|
|
struct ata_host *host;
|
|
int rc;
|
|
|
|
rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
|
|
if (rc)
|
|
return rc;
|
|
*r_host = host;
|
|
|
|
rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
|
|
return rc;
|
|
}
|
|
|
|
host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
|
|
host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
|
|
{
|
|
const struct ata_port_info *ppi[] =
|
|
{ &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
|
|
struct ata_host *host;
|
|
int i, rc;
|
|
|
|
*r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
|
|
if (!host) {
|
|
dev_err(&pdev->dev, "failed to allocate host\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "failed to request/iomap PCI BARs (errno=%d)\n",
|
|
rc);
|
|
return rc;
|
|
}
|
|
host->iomap = pcim_iomap_table(pdev);
|
|
|
|
for (i = 0; i < host->n_ports; i++)
|
|
vt6421_init_addrs(host->ports[i]);
|
|
|
|
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
|
|
if (rc)
|
|
return rc;
|
|
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
|
|
if (rc)
|
|
return rc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
|
|
{
|
|
const struct ata_port_info *ppi[] = { &vt8251_port_info, NULL };
|
|
struct ata_host *host;
|
|
int i, rc;
|
|
|
|
rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
|
|
if (rc)
|
|
return rc;
|
|
*r_host = host;
|
|
|
|
rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
|
|
return rc;
|
|
}
|
|
|
|
/* 8251 hosts four sata ports as M/S of the two channels */
|
|
for (i = 0; i < host->n_ports; i++)
|
|
ata_slave_link_init(host->ports[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void svia_wd_fix(struct pci_dev *pdev)
|
|
{
|
|
u8 tmp8;
|
|
|
|
pci_read_config_byte(pdev, 0x52, &tmp8);
|
|
pci_write_config_byte(pdev, 0x52, tmp8 | BIT(2));
|
|
}
|
|
|
|
static irqreturn_t vt6421_interrupt(int irq, void *dev_instance)
|
|
{
|
|
struct ata_host *host = dev_instance;
|
|
irqreturn_t rc = ata_bmdma_interrupt(irq, dev_instance);
|
|
|
|
/* if the IRQ was not handled, it might be a hotplug IRQ */
|
|
if (rc != IRQ_HANDLED) {
|
|
u32 serror;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
/* check for hotplug on port 0 */
|
|
svia_scr_read(&host->ports[0]->link, SCR_ERROR, &serror);
|
|
if (serror & SERR_PHYRDY_CHG) {
|
|
ata_ehi_hotplugged(&host->ports[0]->link.eh_info);
|
|
ata_port_freeze(host->ports[0]);
|
|
rc = IRQ_HANDLED;
|
|
}
|
|
/* check for hotplug on port 1 */
|
|
svia_scr_read(&host->ports[1]->link, SCR_ERROR, &serror);
|
|
if (serror & SERR_PHYRDY_CHG) {
|
|
ata_ehi_hotplugged(&host->ports[1]->link.eh_info);
|
|
ata_port_freeze(host->ports[1]);
|
|
rc = IRQ_HANDLED;
|
|
}
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
static void vt6421_error_handler(struct ata_port *ap)
|
|
{
|
|
struct svia_priv *hpriv = ap->host->private_data;
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
|
u32 serror;
|
|
|
|
/* see svia_configure() for description */
|
|
if (!hpriv->wd_workaround) {
|
|
svia_scr_read(&ap->link, SCR_ERROR, &serror);
|
|
if (serror == 0x1000500) {
|
|
ata_port_warn(ap, "Incompatible drive: enabling workaround. This slows down transfer rate to ~60 MB/s");
|
|
svia_wd_fix(pdev);
|
|
hpriv->wd_workaround = true;
|
|
ap->link.eh_context.i.flags |= ATA_EHI_QUIET;
|
|
}
|
|
}
|
|
|
|
ata_sff_error_handler(ap);
|
|
}
|
|
|
|
static void svia_configure(struct pci_dev *pdev, int board_id,
|
|
struct svia_priv *hpriv)
|
|
{
|
|
u8 tmp8;
|
|
|
|
pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
|
|
dev_info(&pdev->dev, "routed to hard irq line %d\n",
|
|
(int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
|
|
|
|
/* make sure SATA channels are enabled */
|
|
pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
|
|
if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
|
|
dev_dbg(&pdev->dev, "enabling SATA channels (0x%x)\n",
|
|
(int)tmp8);
|
|
tmp8 |= ALL_PORTS;
|
|
pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
|
|
}
|
|
|
|
/* make sure interrupts for each channel sent to us */
|
|
pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
|
|
if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
|
|
dev_dbg(&pdev->dev, "enabling SATA channel interrupts (0x%x)\n",
|
|
(int) tmp8);
|
|
tmp8 |= ALL_PORTS;
|
|
pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
|
|
}
|
|
|
|
/* make sure native mode is enabled */
|
|
pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
|
|
if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
|
|
dev_dbg(&pdev->dev,
|
|
"enabling SATA channel native mode (0x%x)\n",
|
|
(int) tmp8);
|
|
tmp8 |= NATIVE_MODE_ALL;
|
|
pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
|
|
}
|
|
|
|
/* enable IRQ on hotplug */
|
|
pci_read_config_byte(pdev, SVIA_MISC_3, &tmp8);
|
|
if ((tmp8 & SATA_HOTPLUG) != SATA_HOTPLUG) {
|
|
dev_dbg(&pdev->dev,
|
|
"enabling SATA hotplug (0x%x)\n",
|
|
(int) tmp8);
|
|
tmp8 |= SATA_HOTPLUG;
|
|
pci_write_config_byte(pdev, SVIA_MISC_3, tmp8);
|
|
}
|
|
|
|
/*
|
|
* vt6420/1 has problems talking to some drives. The following
|
|
* is the fix from Joseph Chan <JosephChan@via.com.tw>.
|
|
*
|
|
* When host issues HOLD, device may send up to 20DW of data
|
|
* before acknowledging it with HOLDA and the host should be
|
|
* able to buffer them in FIFO. Unfortunately, some WD drives
|
|
* send up to 40DW before acknowledging HOLD and, in the
|
|
* default configuration, this ends up overflowing vt6421's
|
|
* FIFO, making the controller abort the transaction with
|
|
* R_ERR.
|
|
*
|
|
* Rx52[2] is the internal 128DW FIFO Flow control watermark
|
|
* adjusting mechanism enable bit and the default value 0
|
|
* means host will issue HOLD to device when the left FIFO
|
|
* size goes below 32DW. Setting it to 1 makes the watermark
|
|
* 64DW.
|
|
*
|
|
* https://bugzilla.kernel.org/show_bug.cgi?id=15173
|
|
* http://article.gmane.org/gmane.linux.ide/46352
|
|
* http://thread.gmane.org/gmane.linux.kernel/1062139
|
|
*
|
|
* As the fix slows down data transfer, apply it only if the error
|
|
* actually appears - see vt6421_error_handler()
|
|
* Apply the fix always on vt6420 as we don't know if SCR_ERROR can be
|
|
* read safely.
|
|
*/
|
|
if (board_id == vt6420) {
|
|
svia_wd_fix(pdev);
|
|
hpriv->wd_workaround = true;
|
|
}
|
|
}
|
|
|
|
static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
unsigned int i;
|
|
int rc;
|
|
struct ata_host *host = NULL;
|
|
int board_id = (int) ent->driver_data;
|
|
const unsigned *bar_sizes;
|
|
struct svia_priv *hpriv;
|
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION);
|
|
|
|
rc = pcim_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (board_id == vt6421)
|
|
bar_sizes = &vt6421_bar_sizes[0];
|
|
else
|
|
bar_sizes = &svia_bar_sizes[0];
|
|
|
|
for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
|
|
if ((pci_resource_start(pdev, i) == 0) ||
|
|
(pci_resource_len(pdev, i) < bar_sizes[i])) {
|
|
dev_err(&pdev->dev,
|
|
"invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
|
|
i,
|
|
(unsigned long long)pci_resource_start(pdev, i),
|
|
(unsigned long long)pci_resource_len(pdev, i));
|
|
return -ENODEV;
|
|
}
|
|
|
|
switch (board_id) {
|
|
case vt6420:
|
|
rc = vt6420_prepare_host(pdev, &host);
|
|
break;
|
|
case vt6421:
|
|
rc = vt6421_prepare_host(pdev, &host);
|
|
break;
|
|
case vt8251:
|
|
rc = vt8251_prepare_host(pdev, &host);
|
|
break;
|
|
default:
|
|
rc = -EINVAL;
|
|
}
|
|
if (rc)
|
|
return rc;
|
|
|
|
hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
|
|
if (!hpriv)
|
|
return -ENOMEM;
|
|
host->private_data = hpriv;
|
|
|
|
svia_configure(pdev, board_id, hpriv);
|
|
|
|
pci_set_master(pdev);
|
|
if (board_id == vt6421)
|
|
return ata_host_activate(host, pdev->irq, vt6421_interrupt,
|
|
IRQF_SHARED, &svia_sht);
|
|
else
|
|
return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
|
|
IRQF_SHARED, &svia_sht);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int svia_pci_device_resume(struct pci_dev *pdev)
|
|
{
|
|
struct ata_host *host = pci_get_drvdata(pdev);
|
|
struct svia_priv *hpriv = host->private_data;
|
|
int rc;
|
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (hpriv->wd_workaround)
|
|
svia_wd_fix(pdev);
|
|
ata_host_resume(host);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
module_pci_driver(svia_pci_driver);
|