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This adds basic support for gate-clocks on Rockchip SoCs. There are 16 gates in each register and use the HIWORD_MASK mechanism for changing gate settings. The gate registers form a continuos block which makes the dt node structure a matter of taste, as either all 160 gates can be put into one gate clock spanning all registers or they can be divided into the 10 individual gates containing 16 clocks each. The code supports both approaches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
75 lines
2.2 KiB
Plaintext
75 lines
2.2 KiB
Plaintext
Device Tree Clock bindings for arch-rockchip
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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== Gate clocks ==
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The gate registers form a continuos block which makes the dt node
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structure a matter of taste, as either all gates can be put into
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one gate clock spanning all registers or they can be divided into
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the 10 individual gates containing 16 clocks each.
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The code supports both approaches.
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Required properties:
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- compatible : "rockchip,rk2928-gate-clk"
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- reg : shall be the control register address(es) for the clock.
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- #clock-cells : from common clock binding; shall be set to 1
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- clock-output-names : the corresponding gate names that the clock controls
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- clocks : should contain the parent clock for each individual gate,
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therefore the number of clocks elements should match the number of
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clock-output-names
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Example using multiple gate clocks:
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clk_gates0: gate-clk@200000d0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d0 0x4>;
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clocks = <&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_core_periph", "gate_cpu_gpll",
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"gate_ddrphy", "gate_aclk_cpu",
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"gate_hclk_cpu", "gate_pclk_cpu",
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"gate_atclk_cpu", "gate_i2s0",
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"gate_i2s0_frac", "gate_i2s1",
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"gate_i2s1_frac", "gate_i2s2",
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"gate_i2s2_frac", "gate_spdif",
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"gate_spdif_frac", "gate_testclk";
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#clock-cells = <1>;
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};
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clk_gates1: gate-clk@200000d4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d4 0x4>;
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clocks = <&xin24m>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&dummy>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>;
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clock-output-names =
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"gate_timer0", "gate_timer1",
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"gate_timer2", "gate_jtag",
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"gate_aclk_lcdc1_src", "gate_otgphy0",
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"gate_otgphy1", "gate_ddr_gpll",
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"gate_uart0", "gate_frac_uart0",
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"gate_uart1", "gate_frac_uart1",
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"gate_uart2", "gate_frac_uart2",
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"gate_uart3", "gate_frac_uart3";
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#clock-cells = <1>;
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};
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