mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 13:15:09 +07:00
497d2214e5
* Several patches fixing up incorrectly defined register addresses and
bitfield offsets that could lead to undefined operation when accessing
respective registers or bitfields.
1) clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
2a) clk: samsung: exynos5250: Fix ACP gate register offset
2b) clk: samsung: exynos5250: Add MDMA0 clocks
2c) ARM: dts: exynos5250: Fix MDMA0 clock number
3) clk: samsung: exynos4: Correct SRC_MFC register
All three issues have been present since Exynos5250 and Exynos4 clock
drivers were added by commits 6e3ad26816 ("clk: exynos5250:
register clocks using common clock framework") and e062b57177
("clk: exynos4: register clocks using common clock framework")
respectively.
* Patch to fix automatic disabling of Exynos5250 sysreg clock that could
cause undefined operation of several peripherals, such as USB, I2C,
MIPI or display block.
4) clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
clock
Present since Exynos5250 clock drivers was added by commits
6e3ad26816 ("clk: exynos5250: register clocks using common clock
framework").
* Patch fixing compilation warning in clk-exynos-audss driver when
CONFIG_PM_SLEEP is disabled.
5) clk: exynos: File scope reg_save array should depend on PM_SLEEP
Present since the driver was added by commit 1241ef94cc ("clk:
samsung: register audio subsystem clocks using common clock
framework").
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJSxY6TAAoJEIv3Hb8G/XruUcgP/001H5qqDZWtEk2Z1XvOUPgF
MfFprrNcPpLhLmBnvDpR5mUrcMIp4t/4GcWClmX58zcsZfcQP5YF81oGGiQy+U13
Yu94H+sWihrms5h8GSkqEhB5YSvcIOfs4rtAeNl/g2su7i+l4loF/xofXpj09+qp
xnmKJ8yfB5RD822StgrkoMu7vxzYyK05j8IasSH54vsO9X3Z3jTWuAKdQFKZoZp4
xBGjtIwoyyHndWAlhl1nIj1dvaDgx+gF25qRUrfShfE51R4BNzmvpgiN1mpQTjCl
JpYDJqZ1h7FL883ZXiz7SfRVv4H2GaEWqz+zxgVfHkO45lIL3Eyn1zhSKas4pRFH
KZscKBvT/YEgIQjBW4+VdMuMM0NWIzvYp1BM2/l88KvUgXYiS0EOM5UjYJatKwIO
MW4ZLpIsMiJlN8OygBTaZOZQaY8rbbdVn5KFsgkL0zl7uZzmbYCqhxKrXZfTKyx/
ieEGRmqjrcuguVDPNSsd9TZ/LUm3kTCSzpr3gvAXjK+29DbVrs6fX1lQ0RCxvACQ
8gBjD6ZsVFcsGSbWbPEoDi+qtKielZBjbSrgTDNkRqE/6yqg+UUZVSJJ6kkEA14o
swE+8mGrUhdv5TvpTjJactnBZeUpFbmLm4TE/r695dfwcr6wX7cK41gMVo7bE9fk
2rYzz35ed29q8OfJI/54
=0B0x
-----END PGP SIGNATURE-----
Merge tag 'samsung-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-fixes
Samsung Clock fixes for 3.13-rc7
* Several patches fixing up incorrectly defined register addresses and
bitfield offsets that could lead to undefined operation when accessing
respective registers or bitfields.
1) clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
2a) clk: samsung: exynos5250: Fix ACP gate register offset
2b) clk: samsung: exynos5250: Add MDMA0 clocks
2c) ARM: dts: exynos5250: Fix MDMA0 clock number
3) clk: samsung: exynos4: Correct SRC_MFC register
All three issues have been present since Exynos5250 and Exynos4 clock
drivers were added by commits 6e3ad26816 ("clk: exynos5250:
register clocks using common clock framework") and e062b57177
("clk: exynos4: register clocks using common clock framework")
respectively.
* Patch to fix automatic disabling of Exynos5250 sysreg clock that could
cause undefined operation of several peripherals, such as USB, I2C,
MIPI or display block.
4) clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
clock
Present since Exynos5250 clock drivers was added by commits
6e3ad26816 ("clk: exynos5250: register clocks using common clock
framework").
* Patch fixing compilation warning in clk-exynos-audss driver when
CONFIG_PM_SLEEP is disabled.
5) clk: exynos: File scope reg_save array should depend on PM_SLEEP
Present since the driver was added by commit 1241ef94cc ("clk:
samsung: register audio subsystem clocks using common clock
framework").
192 lines
3.3 KiB
Plaintext
192 lines
3.3 KiB
Plaintext
* Samsung Exynos5250 Clock Controller
|
|
|
|
The Exynos5250 clock controller generates and supplies clock to various
|
|
controllers within the Exynos5250 SoC.
|
|
|
|
Required Properties:
|
|
|
|
- compatible: should be one of the following.
|
|
- "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
|
|
|
|
- reg: physical base address of the controller and length of memory mapped
|
|
region.
|
|
|
|
- #clock-cells: should be 1.
|
|
|
|
The following is the list of clocks generated by the controller. Each clock is
|
|
assigned an identifier and client nodes use this identifier to specify the
|
|
clock which they consume.
|
|
|
|
|
|
[Core Clocks]
|
|
|
|
Clock ID
|
|
----------------------------
|
|
|
|
fin_pll 1
|
|
|
|
[Clock Gate for Special Clocks]
|
|
|
|
Clock ID
|
|
----------------------------
|
|
|
|
sclk_cam_bayer 128
|
|
sclk_cam0 129
|
|
sclk_cam1 130
|
|
sclk_gscl_wa 131
|
|
sclk_gscl_wb 132
|
|
sclk_fimd1 133
|
|
sclk_mipi1 134
|
|
sclk_dp 135
|
|
sclk_hdmi 136
|
|
sclk_pixel 137
|
|
sclk_audio0 138
|
|
sclk_mmc0 139
|
|
sclk_mmc1 140
|
|
sclk_mmc2 141
|
|
sclk_mmc3 142
|
|
sclk_sata 143
|
|
sclk_usb3 144
|
|
sclk_jpeg 145
|
|
sclk_uart0 146
|
|
sclk_uart1 147
|
|
sclk_uart2 148
|
|
sclk_uart3 149
|
|
sclk_pwm 150
|
|
sclk_audio1 151
|
|
sclk_audio2 152
|
|
sclk_spdif 153
|
|
sclk_spi0 154
|
|
sclk_spi1 155
|
|
sclk_spi2 156
|
|
div_i2s1 157
|
|
div_i2s2 158
|
|
sclk_hdmiphy 159
|
|
|
|
|
|
[Peripheral Clock Gates]
|
|
|
|
Clock ID
|
|
----------------------------
|
|
|
|
gscl0 256
|
|
gscl1 257
|
|
gscl2 258
|
|
gscl3 259
|
|
gscl_wa 260
|
|
gscl_wb 261
|
|
smmu_gscl0 262
|
|
smmu_gscl1 263
|
|
smmu_gscl2 264
|
|
smmu_gscl3 265
|
|
mfc 266
|
|
smmu_mfcl 267
|
|
smmu_mfcr 268
|
|
rotator 269
|
|
jpeg 270
|
|
mdma1 271
|
|
smmu_rotator 272
|
|
smmu_jpeg 273
|
|
smmu_mdma1 274
|
|
pdma0 275
|
|
pdma1 276
|
|
sata 277
|
|
usbotg 278
|
|
mipi_hsi 279
|
|
sdmmc0 280
|
|
sdmmc1 281
|
|
sdmmc2 282
|
|
sdmmc3 283
|
|
sromc 284
|
|
usb2 285
|
|
usb3 286
|
|
sata_phyctrl 287
|
|
sata_phyi2c 288
|
|
uart0 289
|
|
uart1 290
|
|
uart2 291
|
|
uart3 292
|
|
uart4 293
|
|
i2c0 294
|
|
i2c1 295
|
|
i2c2 296
|
|
i2c3 297
|
|
i2c4 298
|
|
i2c5 299
|
|
i2c6 300
|
|
i2c7 301
|
|
i2c_hdmi 302
|
|
adc 303
|
|
spi0 304
|
|
spi1 305
|
|
spi2 306
|
|
i2s1 307
|
|
i2s2 308
|
|
pcm1 309
|
|
pcm2 310
|
|
pwm 311
|
|
spdif 312
|
|
ac97 313
|
|
hsi2c0 314
|
|
hsi2c1 315
|
|
hs12c2 316
|
|
hs12c3 317
|
|
chipid 318
|
|
sysreg 319
|
|
pmu 320
|
|
cmu_top 321
|
|
cmu_core 322
|
|
cmu_mem 323
|
|
tzpc0 324
|
|
tzpc1 325
|
|
tzpc2 326
|
|
tzpc3 327
|
|
tzpc4 328
|
|
tzpc5 329
|
|
tzpc6 330
|
|
tzpc7 331
|
|
tzpc8 332
|
|
tzpc9 333
|
|
hdmi_cec 334
|
|
mct 335
|
|
wdt 336
|
|
rtc 337
|
|
tmu 338
|
|
fimd1 339
|
|
mie1 340
|
|
dsim0 341
|
|
dp 342
|
|
mixer 343
|
|
hdmi 344
|
|
g2d 345
|
|
mdma0 346
|
|
smmu_mdma0 347
|
|
|
|
|
|
[Clock Muxes]
|
|
|
|
Clock ID
|
|
----------------------------
|
|
mout_hdmi 1024
|
|
|
|
|
|
Example 1: An example of a clock controller node is listed below.
|
|
|
|
clock: clock-controller@0x10010000 {
|
|
compatible = "samsung,exynos5250-clock";
|
|
reg = <0x10010000 0x30000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
Example 2: UART controller node that consumes the clock generated by the clock
|
|
controller. Refer to the standard clock bindings for information
|
|
about 'clocks' and 'clock-names' property.
|
|
|
|
serial@13820000 {
|
|
compatible = "samsung,exynos4210-uart";
|
|
reg = <0x13820000 0x100>;
|
|
interrupts = <0 54 0>;
|
|
clocks = <&clock 314>, <&clock 153>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|