mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 05:26:44 +07:00
58cf279aca
Infrastructural changes:
- In struct gpio_chip, rename the .dev node to .parent to better reflect
the fact that this is not the GPIO struct device abstraction. We will
add that soon so this would be totallt confusing.
- It was noted that the driver .get_value() callbacks was
sometimes reporting negative -ERR values to the gpiolib core, expecting
them to be propagated to consumer gpiod_get_value() and gpio_get_value()
calls. This was not happening, so as there was a mess of drivers
returning negative errors and some returning "anything else than zero"
to indicate that a line was active. As some would have bit 31 set to
indicate "line active" it clashed with negative error codes. This is
fixed by the largeish series clamping values in all drivers with
!!value to [0,1] and then augmenting the code to propagate error codes
to consumers. (Includes some ACKed patches in other subsystems.)
- Add a void *data pointer to struct gpio_chip. The container_of() design
pattern is indeed very nice, but we want to reform the struct gpio_chip
to be a non-volative, stateless business, and keep states internal to
the gpiolib to be able to hold on to the state when adding a proper
userspace ABI (character device) further down the road. To achieve this,
drivers need a handle at the internal state that is not dependent on
their struct gpio_chip() so we add gpiochip_add_data() and
gpiochip_get_data() following the pattern of many other subsystems.
All the "use gpiochip data pointer" patches transforms drivers to this
scheme.
- The Generic GPIO chip header has been merged into the general
<linux/gpio/driver.h> header, and the custom header for that removed.
Instead of having a separate mm_gpio_chip struct for these generic
drivers, merge that into struct gpio_chip, simplifying the code and
removing the need for separate and confusing includes.
Misc improvements:
- Stabilize the way GPIOs are looked up from the ACPI legacy
specification.
- Incremental driver features for PXA, PCA953X, Lantiq (patches from the
OpenWRT community), RCAR, Zynq, PL061, 104-idi-48
New drivers:
- Add a GPIO chip to the ALSA SoC AC97 driver.
- Add a new Broadcom NSP SoC driver (this lands in the pinctrl dir, but
the branch is merged here too to account for infrastructural changes).
- The sx150x driver now supports the sx1502.
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Merge tag 'gpio-v4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"Here is the bulk of GPIO changes for v4.5.
Notably there are big refactorings mostly by myself, aimed at getting
the gpio_chip into a shape that makes me believe I can proceed to
preserve state for a proper userspace ABI (character device) that has
already been proposed once, but resulted in the feedback that I need
to go back and restructure stuff. So I've been restructuring stuff.
On the way I ran into brokenness (return code from the get_value()
callback) and had to fix it. Also, refactored generic GPIO to be
simpler.
Some of that is still waiting to trickle down from the subsystems all
over the kernel that provide random gpio_chips, I've touched every
single GPIO driver in the kernel now, oh man I didn't know I was
responsible for so much...
Apart from that we're churning along as usual.
I took some effort to test and retest so it should merge nicely and we
shook out a couple of bugs in -next.
Infrastructural changes:
- In struct gpio_chip, rename the .dev node to .parent to better
reflect the fact that this is not the GPIO struct device
abstraction. We will add that soon so this would be totallt
confusing.
- It was noted that the driver .get_value() callbacks was sometimes
reporting negative -ERR values to the gpiolib core, expecting them
to be propagated to consumer gpiod_get_value() and gpio_get_value()
calls. This was not happening, so as there was a mess of drivers
returning negative errors and some returning "anything else than
zero" to indicate that a line was active. As some would have bit
31 set to indicate "line active" it clashed with negative error
codes. This is fixed by the largeish series clamping values in all
drivers with !!value to [0,1] and then augmenting the code to
propagate error codes to consumers. (Includes some ACKed patches
in other subsystems.)
- Add a void *data pointer to struct gpio_chip. The container_of()
design pattern is indeed very nice, but we want to reform the
struct gpio_chip to be a non-volative, stateless business, and keep
states internal to the gpiolib to be able to hold on to the state
when adding a proper userspace ABI (character device) further down
the road. To achieve this, drivers need a handle at the internal
state that is not dependent on their struct gpio_chip() so we add
gpiochip_add_data() and gpiochip_get_data() following the pattern
of many other subsystems. All the "use gpiochip data pointer"
patches transforms drivers to this scheme.
- The Generic GPIO chip header has been merged into the general
<linux/gpio/driver.h> header, and the custom header for that
removed. Instead of having a separate mm_gpio_chip struct for
these generic drivers, merge that into struct gpio_chip,
simplifying the code and removing the need for separate and
confusing includes.
Misc improvements:
- Stabilize the way GPIOs are looked up from the ACPI legacy
specification.
- Incremental driver features for PXA, PCA953X, Lantiq (patches from
the OpenWRT community), RCAR, Zynq, PL061, 104-idi-48
New drivers:
- Add a GPIO chip to the ALSA SoC AC97 driver.
- Add a new Broadcom NSP SoC driver (this lands in the pinctrl dir,
but the branch is merged here too to account for infrastructural
changes).
- The sx150x driver now supports the sx1502"
* tag 'gpio-v4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (220 commits)
gpio: generic: make bgpio_pdata always visible
gpiolib: fix chip order in gpio list
gpio: mpc8xxx: Do not use gpiochip_get_data() in mpc8xxx_gpio_save_regs()
gpio: mm-lantiq: Do not use gpiochip_get_data() in ltq_mm_save_regs()
gpio: brcmstb: Allow building driver for BMIPS_GENERIC
gpio: brcmstb: Set endian flags for big-endian MIPS
gpio: moxart: fix build regression
gpio: xilinx: Do not use gpiochip_get_data() in xgpio_save_regs()
leds: pca9532: use gpiochip data pointer
leds: tca6507: use gpiochip data pointer
hid: cp2112: use gpiochip data pointer
bcma: gpio: use gpiochip data pointer
avr32: gpio: use gpiochip data pointer
video: fbdev: via: use gpiochip data pointer
gpio: pch: Optimize pch_gpio_get()
Revert "pinctrl: lantiq: Implement gpio_chip.to_irq"
pinctrl: nsp-gpio: use gpiochip data pointer
pinctrl: vt8500-wmt: use gpiochip data pointer
pinctrl: exynos5440: use gpiochip data pointer
pinctrl: at91-pio4: use gpiochip data pointer
...
1632 lines
55 KiB
C
1632 lines
55 KiB
C
/*
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* Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2012 Linaro Ltd
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* http://www.linaro.org
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*
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This file contains the Samsung Exynos specific information required by the
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* the Samsung pinctrl/gpiolib driver. It also includes the implementation of
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* external gpio and wakeup interrupt support.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include "pinctrl-samsung.h"
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#include "pinctrl-exynos.h"
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struct exynos_irq_chip {
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struct irq_chip chip;
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u32 eint_con;
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u32 eint_mask;
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u32 eint_pend;
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};
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static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
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{
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return container_of(chip, struct exynos_irq_chip, chip);
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}
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static const struct samsung_pin_bank_type bank_type_off = {
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.fld_width = { 4, 1, 2, 2, 2, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
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};
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static const struct samsung_pin_bank_type bank_type_alive = {
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.fld_width = { 4, 1, 2, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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static void exynos_irq_mask(struct irq_data *irqd)
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{
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struct irq_chip *chip = irq_data_get_irq_chip(irqd);
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struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
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unsigned long mask;
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unsigned long flags;
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spin_lock_irqsave(&bank->slock, flags);
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mask = readl(d->virt_base + reg_mask);
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mask |= 1 << irqd->hwirq;
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writel(mask, d->virt_base + reg_mask);
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spin_unlock_irqrestore(&bank->slock, flags);
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}
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static void exynos_irq_ack(struct irq_data *irqd)
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{
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struct irq_chip *chip = irq_data_get_irq_chip(irqd);
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struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
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writel(1 << irqd->hwirq, d->virt_base + reg_pend);
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}
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static void exynos_irq_unmask(struct irq_data *irqd)
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{
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struct irq_chip *chip = irq_data_get_irq_chip(irqd);
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struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
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unsigned long mask;
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unsigned long flags;
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/*
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* Ack level interrupts right before unmask
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*
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* If we don't do this we'll get a double-interrupt. Level triggered
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* interrupts must not fire an interrupt if the level is not
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* _currently_ active, even if it was active while the interrupt was
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* masked.
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*/
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if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
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exynos_irq_ack(irqd);
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spin_lock_irqsave(&bank->slock, flags);
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mask = readl(d->virt_base + reg_mask);
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mask &= ~(1 << irqd->hwirq);
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writel(mask, d->virt_base + reg_mask);
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spin_unlock_irqrestore(&bank->slock, flags);
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}
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static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
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{
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struct irq_chip *chip = irq_data_get_irq_chip(irqd);
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struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
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unsigned int con, trig_type;
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unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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trig_type = EXYNOS_EINT_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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trig_type = EXYNOS_EINT_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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trig_type = EXYNOS_EINT_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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trig_type = EXYNOS_EINT_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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trig_type = EXYNOS_EINT_LEVEL_LOW;
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break;
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default:
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pr_err("unsupported external interrupt type\n");
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return -EINVAL;
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}
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if (type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(irqd, handle_edge_irq);
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else
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irq_set_handler_locked(irqd, handle_level_irq);
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con = readl(d->virt_base + reg_con);
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con &= ~(EXYNOS_EINT_CON_MASK << shift);
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con |= trig_type << shift;
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writel(con, d->virt_base + reg_con);
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return 0;
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}
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static int exynos_irq_request_resources(struct irq_data *irqd)
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{
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struct irq_chip *chip = irq_data_get_irq_chip(irqd);
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struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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const struct samsung_pin_bank_type *bank_type = bank->type;
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
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unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
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unsigned long flags;
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unsigned int mask;
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unsigned int con;
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int ret;
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ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
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if (ret) {
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dev_err(bank->gpio_chip.parent,
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"unable to lock pin %s-%lu IRQ\n",
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bank->name, irqd->hwirq);
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return ret;
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}
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reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
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shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
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mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
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spin_lock_irqsave(&bank->slock, flags);
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con = readl(d->virt_base + reg_con);
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con &= ~(mask << shift);
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con |= EXYNOS_EINT_FUNC << shift;
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writel(con, d->virt_base + reg_con);
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spin_unlock_irqrestore(&bank->slock, flags);
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exynos_irq_unmask(irqd);
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return 0;
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}
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static void exynos_irq_release_resources(struct irq_data *irqd)
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{
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struct irq_chip *chip = irq_data_get_irq_chip(irqd);
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struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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const struct samsung_pin_bank_type *bank_type = bank->type;
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
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unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
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unsigned long flags;
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unsigned int mask;
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unsigned int con;
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reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
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shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
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mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
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exynos_irq_mask(irqd);
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spin_lock_irqsave(&bank->slock, flags);
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con = readl(d->virt_base + reg_con);
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con &= ~(mask << shift);
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con |= FUNC_INPUT << shift;
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writel(con, d->virt_base + reg_con);
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spin_unlock_irqrestore(&bank->slock, flags);
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gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
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}
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/*
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* irq_chip for gpio interrupts.
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*/
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static struct exynos_irq_chip exynos_gpio_irq_chip = {
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.chip = {
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.name = "exynos_gpio_irq_chip",
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.irq_unmask = exynos_irq_unmask,
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.irq_mask = exynos_irq_mask,
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.irq_ack = exynos_irq_ack,
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.irq_set_type = exynos_irq_set_type,
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.irq_request_resources = exynos_irq_request_resources,
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.irq_release_resources = exynos_irq_release_resources,
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},
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.eint_con = EXYNOS_GPIO_ECON_OFFSET,
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.eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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};
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static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct samsung_pin_bank *b = h->host_data;
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irq_set_chip_data(virq, b);
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irq_set_chip_and_handler(virq, &b->irq_chip->chip,
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handle_level_irq);
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return 0;
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}
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/*
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* irq domain callbacks for external gpio and wakeup interrupt controllers.
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*/
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static const struct irq_domain_ops exynos_eint_irqd_ops = {
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.map = exynos_eint_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
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{
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struct samsung_pinctrl_drv_data *d = data;
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struct samsung_pin_bank *bank = d->pin_banks;
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unsigned int svc, group, pin, virq;
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svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
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group = EXYNOS_SVC_GROUP(svc);
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pin = svc & EXYNOS_SVC_NUM_MASK;
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if (!group)
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return IRQ_HANDLED;
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bank += (group - 1);
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virq = irq_linear_revmap(bank->irq_domain, pin);
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if (!virq)
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return IRQ_NONE;
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generic_handle_irq(virq);
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return IRQ_HANDLED;
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}
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struct exynos_eint_gpio_save {
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u32 eint_con;
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u32 eint_fltcon0;
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u32 eint_fltcon1;
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};
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/*
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* exynos_eint_gpio_init() - setup handling of external gpio interrupts.
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* @d: driver data of samsung pinctrl driver.
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*/
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static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
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{
|
|
struct samsung_pin_bank *bank;
|
|
struct device *dev = d->dev;
|
|
int ret;
|
|
int i;
|
|
|
|
if (!d->irq) {
|
|
dev_err(dev, "irq number not available\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
|
|
0, dev_name(dev), d);
|
|
if (ret) {
|
|
dev_err(dev, "irq request failed\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
bank = d->pin_banks;
|
|
for (i = 0; i < d->nr_banks; ++i, ++bank) {
|
|
if (bank->eint_type != EINT_TYPE_GPIO)
|
|
continue;
|
|
bank->irq_domain = irq_domain_add_linear(bank->of_node,
|
|
bank->nr_pins, &exynos_eint_irqd_ops, bank);
|
|
if (!bank->irq_domain) {
|
|
dev_err(dev, "gpio irq domain add failed\n");
|
|
ret = -ENXIO;
|
|
goto err_domains;
|
|
}
|
|
|
|
bank->soc_priv = devm_kzalloc(d->dev,
|
|
sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
|
|
if (!bank->soc_priv) {
|
|
irq_domain_remove(bank->irq_domain);
|
|
ret = -ENOMEM;
|
|
goto err_domains;
|
|
}
|
|
|
|
bank->irq_chip = &exynos_gpio_irq_chip;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_domains:
|
|
for (--i, --bank; i >= 0; --i, --bank) {
|
|
if (bank->eint_type != EINT_TYPE_GPIO)
|
|
continue;
|
|
irq_domain_remove(bank->irq_domain);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static u32 exynos_eint_wake_mask = 0xffffffff;
|
|
|
|
u32 exynos_get_eint_wake_mask(void)
|
|
{
|
|
return exynos_eint_wake_mask;
|
|
}
|
|
|
|
static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
|
|
{
|
|
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
|
|
unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
|
|
|
|
pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
|
|
|
|
if (!on)
|
|
exynos_eint_wake_mask |= bit;
|
|
else
|
|
exynos_eint_wake_mask &= ~bit;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* irq_chip for wakeup interrupts
|
|
*/
|
|
static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
|
|
.chip = {
|
|
.name = "exynos4210_wkup_irq_chip",
|
|
.irq_unmask = exynos_irq_unmask,
|
|
.irq_mask = exynos_irq_mask,
|
|
.irq_ack = exynos_irq_ack,
|
|
.irq_set_type = exynos_irq_set_type,
|
|
.irq_set_wake = exynos_wkup_irq_set_wake,
|
|
.irq_request_resources = exynos_irq_request_resources,
|
|
.irq_release_resources = exynos_irq_release_resources,
|
|
},
|
|
.eint_con = EXYNOS_WKUP_ECON_OFFSET,
|
|
.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
|
|
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
|
|
};
|
|
|
|
static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
|
|
.chip = {
|
|
.name = "exynos7_wkup_irq_chip",
|
|
.irq_unmask = exynos_irq_unmask,
|
|
.irq_mask = exynos_irq_mask,
|
|
.irq_ack = exynos_irq_ack,
|
|
.irq_set_type = exynos_irq_set_type,
|
|
.irq_set_wake = exynos_wkup_irq_set_wake,
|
|
.irq_request_resources = exynos_irq_request_resources,
|
|
.irq_release_resources = exynos_irq_release_resources,
|
|
},
|
|
.eint_con = EXYNOS7_WKUP_ECON_OFFSET,
|
|
.eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
|
|
.eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
|
|
};
|
|
|
|
/* list of external wakeup controllers supported */
|
|
static const struct of_device_id exynos_wkup_irq_ids[] = {
|
|
{ .compatible = "samsung,exynos4210-wakeup-eint",
|
|
.data = &exynos4210_wkup_irq_chip },
|
|
{ .compatible = "samsung,exynos7-wakeup-eint",
|
|
.data = &exynos7_wkup_irq_chip },
|
|
{ }
|
|
};
|
|
|
|
/* interrupt handler for wakeup interrupts 0..15 */
|
|
static void exynos_irq_eint0_15(struct irq_desc *desc)
|
|
{
|
|
struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
|
|
struct samsung_pin_bank *bank = eintd->bank;
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
int eint_irq;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
chip->irq_mask(&desc->irq_data);
|
|
|
|
if (chip->irq_ack)
|
|
chip->irq_ack(&desc->irq_data);
|
|
|
|
eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
|
|
generic_handle_irq(eint_irq);
|
|
chip->irq_unmask(&desc->irq_data);
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static inline void exynos_irq_demux_eint(unsigned long pend,
|
|
struct irq_domain *domain)
|
|
{
|
|
unsigned int irq;
|
|
|
|
while (pend) {
|
|
irq = fls(pend) - 1;
|
|
generic_handle_irq(irq_find_mapping(domain, irq));
|
|
pend &= ~(1 << irq);
|
|
}
|
|
}
|
|
|
|
/* interrupt handler for wakeup interrupt 16 */
|
|
static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
|
|
{
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
|
|
struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
|
|
unsigned long pend;
|
|
unsigned long mask;
|
|
int i;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
for (i = 0; i < eintd->nr_banks; ++i) {
|
|
struct samsung_pin_bank *b = eintd->banks[i];
|
|
pend = readl(d->virt_base + b->irq_chip->eint_pend
|
|
+ b->eint_offset);
|
|
mask = readl(d->virt_base + b->irq_chip->eint_mask
|
|
+ b->eint_offset);
|
|
exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
/*
|
|
* exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
|
|
* @d: driver data of samsung pinctrl driver.
|
|
*/
|
|
static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
|
|
{
|
|
struct device *dev = d->dev;
|
|
struct device_node *wkup_np = NULL;
|
|
struct device_node *np;
|
|
struct samsung_pin_bank *bank;
|
|
struct exynos_weint_data *weint_data;
|
|
struct exynos_muxed_weint_data *muxed_data;
|
|
struct exynos_irq_chip *irq_chip;
|
|
unsigned int muxed_banks = 0;
|
|
unsigned int i;
|
|
int idx, irq;
|
|
|
|
for_each_child_of_node(dev->of_node, np) {
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_node(exynos_wkup_irq_ids, np);
|
|
if (match) {
|
|
irq_chip = kmemdup(match->data,
|
|
sizeof(*irq_chip), GFP_KERNEL);
|
|
wkup_np = np;
|
|
break;
|
|
}
|
|
}
|
|
if (!wkup_np)
|
|
return -ENODEV;
|
|
|
|
bank = d->pin_banks;
|
|
for (i = 0; i < d->nr_banks; ++i, ++bank) {
|
|
if (bank->eint_type != EINT_TYPE_WKUP)
|
|
continue;
|
|
|
|
bank->irq_domain = irq_domain_add_linear(bank->of_node,
|
|
bank->nr_pins, &exynos_eint_irqd_ops, bank);
|
|
if (!bank->irq_domain) {
|
|
dev_err(dev, "wkup irq domain add failed\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
bank->irq_chip = irq_chip;
|
|
|
|
if (!of_find_property(bank->of_node, "interrupts", NULL)) {
|
|
bank->eint_type = EINT_TYPE_WKUP_MUX;
|
|
++muxed_banks;
|
|
continue;
|
|
}
|
|
|
|
weint_data = devm_kzalloc(dev, bank->nr_pins
|
|
* sizeof(*weint_data), GFP_KERNEL);
|
|
if (!weint_data) {
|
|
dev_err(dev, "could not allocate memory for weint_data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
for (idx = 0; idx < bank->nr_pins; ++idx) {
|
|
irq = irq_of_parse_and_map(bank->of_node, idx);
|
|
if (!irq) {
|
|
dev_err(dev, "irq number for eint-%s-%d not found\n",
|
|
bank->name, idx);
|
|
continue;
|
|
}
|
|
weint_data[idx].irq = idx;
|
|
weint_data[idx].bank = bank;
|
|
irq_set_chained_handler_and_data(irq,
|
|
exynos_irq_eint0_15,
|
|
&weint_data[idx]);
|
|
}
|
|
}
|
|
|
|
if (!muxed_banks)
|
|
return 0;
|
|
|
|
irq = irq_of_parse_and_map(wkup_np, 0);
|
|
if (!irq) {
|
|
dev_err(dev, "irq number for muxed EINTs not found\n");
|
|
return 0;
|
|
}
|
|
|
|
muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
|
|
+ muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
|
|
if (!muxed_data) {
|
|
dev_err(dev, "could not allocate memory for muxed_data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
|
|
muxed_data);
|
|
|
|
bank = d->pin_banks;
|
|
idx = 0;
|
|
for (i = 0; i < d->nr_banks; ++i, ++bank) {
|
|
if (bank->eint_type != EINT_TYPE_WKUP_MUX)
|
|
continue;
|
|
|
|
muxed_data->banks[idx++] = bank;
|
|
}
|
|
muxed_data->nr_banks = muxed_banks;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void exynos_pinctrl_suspend_bank(
|
|
struct samsung_pinctrl_drv_data *drvdata,
|
|
struct samsung_pin_bank *bank)
|
|
{
|
|
struct exynos_eint_gpio_save *save = bank->soc_priv;
|
|
void __iomem *regs = drvdata->virt_base;
|
|
|
|
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
|
|
+ bank->eint_offset);
|
|
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
|
+ 2 * bank->eint_offset);
|
|
save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
|
+ 2 * bank->eint_offset + 4);
|
|
|
|
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
|
|
pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
|
|
pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
|
|
}
|
|
|
|
static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
|
|
{
|
|
struct samsung_pin_bank *bank = drvdata->pin_banks;
|
|
int i;
|
|
|
|
for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
|
|
if (bank->eint_type == EINT_TYPE_GPIO)
|
|
exynos_pinctrl_suspend_bank(drvdata, bank);
|
|
}
|
|
|
|
static void exynos_pinctrl_resume_bank(
|
|
struct samsung_pinctrl_drv_data *drvdata,
|
|
struct samsung_pin_bank *bank)
|
|
{
|
|
struct exynos_eint_gpio_save *save = bank->soc_priv;
|
|
void __iomem *regs = drvdata->virt_base;
|
|
|
|
pr_debug("%s: con %#010x => %#010x\n", bank->name,
|
|
readl(regs + EXYNOS_GPIO_ECON_OFFSET
|
|
+ bank->eint_offset), save->eint_con);
|
|
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
|
|
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
|
+ 2 * bank->eint_offset), save->eint_fltcon0);
|
|
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
|
|
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
|
+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
|
|
|
|
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
|
|
+ bank->eint_offset);
|
|
writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
|
+ 2 * bank->eint_offset);
|
|
writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
|
+ 2 * bank->eint_offset + 4);
|
|
}
|
|
|
|
static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
|
|
{
|
|
struct samsung_pin_bank *bank = drvdata->pin_banks;
|
|
int i;
|
|
|
|
for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
|
|
if (bank->eint_type == EINT_TYPE_GPIO)
|
|
exynos_pinctrl_resume_bank(drvdata, bank);
|
|
}
|
|
|
|
/* pin banks of s5pv210 pin-controller */
|
|
static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
|
|
EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
|
|
EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
|
|
};
|
|
|
|
const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = s5pv210_pin_bank,
|
|
.nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
},
|
|
};
|
|
|
|
/* pin banks of exynos3250 pin-controller 0 */
|
|
static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
|
|
};
|
|
|
|
/* pin banks of exynos3250 pin-controller 1 */
|
|
static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
|
|
EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
|
|
* two gpio/pin-mux/pinconfig controllers.
|
|
*/
|
|
const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = exynos3250_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = exynos3250_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
},
|
|
};
|
|
|
|
/* pin banks of exynos4210 pin-controller 0 */
|
|
static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
|
|
};
|
|
|
|
/* pin banks of exynos4210 pin-controller 1 */
|
|
static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
|
|
EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
|
|
};
|
|
|
|
/* pin banks of exynos4210 pin-controller 2 */
|
|
static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
|
|
* three gpio/pin-mux/pinconfig controllers.
|
|
*/
|
|
const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = exynos4210_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = exynos4210_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 2 data */
|
|
.pin_banks = exynos4210_pin_banks2,
|
|
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
|
|
},
|
|
};
|
|
|
|
/* pin banks of exynos4x12 pin-controller 0 */
|
|
static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
|
|
};
|
|
|
|
/* pin banks of exynos4x12 pin-controller 1 */
|
|
static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
|
|
EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
|
|
};
|
|
|
|
/* pin banks of exynos4x12 pin-controller 2 */
|
|
static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos4x12 pin-controller 3 */
|
|
static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
|
|
* four gpio/pin-mux/pinconfig controllers.
|
|
*/
|
|
const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = exynos4x12_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = exynos4x12_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 2 data */
|
|
.pin_banks = exynos4x12_pin_banks2,
|
|
.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 3 data */
|
|
.pin_banks = exynos4x12_pin_banks3,
|
|
.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
},
|
|
};
|
|
|
|
/* pin banks of exynos4415 pin-controller 0 */
|
|
static const struct samsung_pin_bank_data exynos4415_pin_banks0[] = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
|
|
EXYNOS_PIN_BANK_EINTG(1, 0x1C0, "gpf2", 0x38),
|
|
};
|
|
|
|
/* pin banks of exynos4415 pin-controller 1 */
|
|
static const struct samsung_pin_bank_data exynos4415_pin_banks1[] = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpl0", 0x18),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x120, "mp00"),
|
|
EXYNOS_PIN_BANK_EINTN(4, 0x140, "mp01"),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x160, "mp02"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x180, "mp03"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "mp04"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "mp05"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "mp06"),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
|
|
};
|
|
|
|
/* pin banks of exynos4415 pin-controller 2 */
|
|
static const struct samsung_pin_bank_data exynos4415_pin_banks2[] = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
|
|
EXYNOS_PIN_BANK_EINTN(2, 0x000, "etc1"),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for Exynos4415 SoC. Exynos4415 SoC includes
|
|
* three gpio/pin-mux/pinconfig controllers.
|
|
*/
|
|
const struct samsung_pin_ctrl exynos4415_pin_ctrl[] = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = exynos4415_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos4415_pin_banks0),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = exynos4415_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos4415_pin_banks1),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 2 data */
|
|
.pin_banks = exynos4415_pin_banks2,
|
|
.nr_banks = ARRAY_SIZE(exynos4415_pin_banks2),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
},
|
|
};
|
|
|
|
/* pin banks of exynos5250 pin-controller 0 */
|
|
static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
|
|
EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
|
|
};
|
|
|
|
/* pin banks of exynos5250 pin-controller 1 */
|
|
static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
|
|
};
|
|
|
|
/* pin banks of exynos5250 pin-controller 2 */
|
|
static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
|
|
};
|
|
|
|
/* pin banks of exynos5250 pin-controller 3 */
|
|
static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
|
|
* four gpio/pin-mux/pinconfig controllers.
|
|
*/
|
|
const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = exynos5250_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = exynos5250_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 2 data */
|
|
.pin_banks = exynos5250_pin_banks2,
|
|
.nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 3 data */
|
|
.pin_banks = exynos5250_pin_banks3,
|
|
.nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
},
|
|
};
|
|
|
|
/* pin banks of exynos5260 pin-controller 0 */
|
|
static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
|
|
};
|
|
|
|
/* pin banks of exynos5260 pin-controller 1 */
|
|
static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
|
|
};
|
|
|
|
/* pin banks of exynos5260 pin-controller 2 */
|
|
static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
|
|
* three gpio/pin-mux/pinconfig controllers.
|
|
*/
|
|
const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = exynos5260_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
}, {
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = exynos5260_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 2 data */
|
|
.pin_banks = exynos5260_pin_banks2,
|
|
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
},
|
|
};
|
|
|
|
/* pin banks of exynos5410 pin-controller 0 */
|
|
static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
|
|
EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
|
|
EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
|
|
};
|
|
|
|
/* pin banks of exynos5410 pin-controller 1 */
|
|
static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
|
|
};
|
|
|
|
/* pin banks of exynos5410 pin-controller 2 */
|
|
static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
|
|
};
|
|
|
|
/* pin banks of exynos5410 pin-controller 3 */
|
|
static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
|
|
* four gpio/pin-mux/pinconfig controllers.
|
|
*/
|
|
const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = exynos5410_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = exynos5410_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 2 data */
|
|
.pin_banks = exynos5410_pin_banks2,
|
|
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 3 data */
|
|
.pin_banks = exynos5410_pin_banks3,
|
|
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
},
|
|
};
|
|
|
|
/* pin banks of exynos5420 pin-controller 0 */
|
|
static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
|
|
};
|
|
|
|
/* pin banks of exynos5420 pin-controller 1 */
|
|
static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
|
|
EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
|
|
EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
|
|
EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
|
|
};
|
|
|
|
/* pin banks of exynos5420 pin-controller 2 */
|
|
static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
|
|
};
|
|
|
|
/* pin banks of exynos5420 pin-controller 3 */
|
|
static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
|
|
};
|
|
|
|
/* pin banks of exynos5420 pin-controller 4 */
|
|
static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
|
|
* four gpio/pin-mux/pinconfig controllers.
|
|
*/
|
|
const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = exynos5420_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
}, {
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = exynos5420_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 2 data */
|
|
.pin_banks = exynos5420_pin_banks2,
|
|
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 3 data */
|
|
.pin_banks = exynos5420_pin_banks3,
|
|
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 4 data */
|
|
.pin_banks = exynos5420_pin_banks4,
|
|
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
},
|
|
};
|
|
|
|
/* pin banks of exynos5433 pin-controller - ALIVE */
|
|
static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
|
|
EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
|
|
};
|
|
|
|
/* pin banks of exynos5433 pin-controller - AUD */
|
|
static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
|
|
};
|
|
|
|
/* pin banks of exynos5433 pin-controller - CPIF */
|
|
static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos5433 pin-controller - eSE */
|
|
static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {
|
|
EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos5433 pin-controller - FINGER */
|
|
static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos5433 pin-controller - FSYS */
|
|
static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
|
|
};
|
|
|
|
/* pin banks of exynos5433 pin-controller - IMEM */
|
|
static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos5433 pin-controller - NFC */
|
|
static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {
|
|
EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos5433 pin-controller - PERIC */
|
|
static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
|
|
};
|
|
|
|
/* pin banks of exynos5433 pin-controller - TOUCH */
|
|
static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {
|
|
EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
|
|
* ten gpio/pin-mux/pinconfig controllers.
|
|
*/
|
|
const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = exynos5433_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = exynos5433_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos5433_pin_banks1),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 2 data */
|
|
.pin_banks = exynos5433_pin_banks2,
|
|
.nr_banks = ARRAY_SIZE(exynos5433_pin_banks2),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 3 data */
|
|
.pin_banks = exynos5433_pin_banks3,
|
|
.nr_banks = ARRAY_SIZE(exynos5433_pin_banks3),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 4 data */
|
|
.pin_banks = exynos5433_pin_banks4,
|
|
.nr_banks = ARRAY_SIZE(exynos5433_pin_banks4),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 5 data */
|
|
.pin_banks = exynos5433_pin_banks5,
|
|
.nr_banks = ARRAY_SIZE(exynos5433_pin_banks5),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 6 data */
|
|
.pin_banks = exynos5433_pin_banks6,
|
|
.nr_banks = ARRAY_SIZE(exynos5433_pin_banks6),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 7 data */
|
|
.pin_banks = exynos5433_pin_banks7,
|
|
.nr_banks = ARRAY_SIZE(exynos5433_pin_banks7),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 8 data */
|
|
.pin_banks = exynos5433_pin_banks8,
|
|
.nr_banks = ARRAY_SIZE(exynos5433_pin_banks8),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
}, {
|
|
/* pin-controller instance 9 data */
|
|
.pin_banks = exynos5433_pin_banks9,
|
|
.nr_banks = ARRAY_SIZE(exynos5433_pin_banks9),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.suspend = exynos_pinctrl_suspend,
|
|
.resume = exynos_pinctrl_resume,
|
|
},
|
|
};
|
|
|
|
/* pin banks of exynos7 pin-controller - ALIVE */
|
|
static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
|
|
};
|
|
|
|
/* pin banks of exynos7 pin-controller - BUS0 */
|
|
static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
|
|
EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
|
|
EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
|
|
};
|
|
|
|
/* pin banks of exynos7 pin-controller - NFC */
|
|
static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos7 pin-controller - TOUCH */
|
|
static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos7 pin-controller - FF */
|
|
static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos7 pin-controller - ESE */
|
|
static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos7 pin-controller - FSYS0 */
|
|
static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
|
|
};
|
|
|
|
/* pin banks of exynos7 pin-controller - FSYS1 */
|
|
static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
|
|
};
|
|
|
|
/* pin banks of exynos7 pin-controller - BUS1 */
|
|
static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
|
|
EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
|
|
EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
|
|
EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
|
|
EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
|
|
};
|
|
|
|
static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
|
|
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
|
|
EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
|
|
};
|
|
|
|
const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
|
|
{
|
|
/* pin-controller instance 0 Alive data */
|
|
.pin_banks = exynos7_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
}, {
|
|
/* pin-controller instance 1 BUS0 data */
|
|
.pin_banks = exynos7_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos7_pin_banks1),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 2 NFC data */
|
|
.pin_banks = exynos7_pin_banks2,
|
|
.nr_banks = ARRAY_SIZE(exynos7_pin_banks2),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 3 TOUCH data */
|
|
.pin_banks = exynos7_pin_banks3,
|
|
.nr_banks = ARRAY_SIZE(exynos7_pin_banks3),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 4 FF data */
|
|
.pin_banks = exynos7_pin_banks4,
|
|
.nr_banks = ARRAY_SIZE(exynos7_pin_banks4),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 5 ESE data */
|
|
.pin_banks = exynos7_pin_banks5,
|
|
.nr_banks = ARRAY_SIZE(exynos7_pin_banks5),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 6 FSYS0 data */
|
|
.pin_banks = exynos7_pin_banks6,
|
|
.nr_banks = ARRAY_SIZE(exynos7_pin_banks6),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 7 FSYS1 data */
|
|
.pin_banks = exynos7_pin_banks7,
|
|
.nr_banks = ARRAY_SIZE(exynos7_pin_banks7),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 8 BUS1 data */
|
|
.pin_banks = exynos7_pin_banks8,
|
|
.nr_banks = ARRAY_SIZE(exynos7_pin_banks8),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
}, {
|
|
/* pin-controller instance 9 AUD data */
|
|
.pin_banks = exynos7_pin_banks9,
|
|
.nr_banks = ARRAY_SIZE(exynos7_pin_banks9),
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
},
|
|
};
|