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494fc42170
__get_cpu_var() is used for multiple purposes in the kernel source. One of them is address calculation via the form &__get_cpu_var(x). This calculates the address for the instance of the percpu variable of the current processor based on an offset. Other use cases are for storing and retrieving data from the current processors percpu area. __get_cpu_var() can be used as an lvalue when writing data or on the right side of an assignment. __get_cpu_var() is defined as : #define __get_cpu_var(var) (*this_cpu_ptr(&(var))) __get_cpu_var() always only does an address determination. However, store and retrieve operations could use a segment prefix (or global register on other platforms) to avoid the address calculation. this_cpu_write() and this_cpu_read() can directly take an offset into a percpu area and use optimized assembly code to read and write per cpu variables. This patch converts __get_cpu_var into either an explicit address calculation using this_cpu_ptr() or into a use of this_cpu operations that use the offset. Thereby address calculations are avoided and less registers are used when code is generated. At the end of the patch set all uses of __get_cpu_var have been removed so the macro is removed too. The patch set includes passes over all arches as well. Once these operations are used throughout then specialized macros can be defined in non -x86 arches as well in order to optimize per cpu access by f.e. using a global register that may be set to the per cpu base. Transformations done to __get_cpu_var() 1. Determine the address of the percpu instance of the current processor. DEFINE_PER_CPU(int, y); int *x = &__get_cpu_var(y); Converts to int *x = this_cpu_ptr(&y); 2. Same as #1 but this time an array structure is involved. DEFINE_PER_CPU(int, y[20]); int *x = __get_cpu_var(y); Converts to int *x = this_cpu_ptr(y); 3. Retrieve the content of the current processors instance of a per cpu variable. DEFINE_PER_CPU(int, y); int x = __get_cpu_var(y) Converts to int x = __this_cpu_read(y); 4. Retrieve the content of a percpu struct DEFINE_PER_CPU(struct mystruct, y); struct mystruct x = __get_cpu_var(y); Converts to memcpy(&x, this_cpu_ptr(&y), sizeof(x)); 5. Assignment to a per cpu variable DEFINE_PER_CPU(int, y) __get_cpu_var(y) = x; Converts to __this_cpu_write(y, x); 6. Increment/Decrement etc of a per cpu variable DEFINE_PER_CPU(int, y); __get_cpu_var(y)++ Converts to __this_cpu_inc(y) Cc: sparclinux@vger.kernel.org Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Christoph Lameter <cl@linux.com> Signed-off-by: Tejun Heo <tj@kernel.org>
1025 lines
24 KiB
C
1025 lines
24 KiB
C
/* pci_sun4v.c: SUN4V specific PCI controller support.
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*
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* Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/export.h>
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#include <linux/log2.h>
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#include <linux/of_device.h>
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#include <asm/iommu.h>
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#include <asm/irq.h>
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#include <asm/hypervisor.h>
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#include <asm/prom.h>
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#include "pci_impl.h"
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#include "iommu_common.h"
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#include "pci_sun4v.h"
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#define DRIVER_NAME "pci_sun4v"
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#define PFX DRIVER_NAME ": "
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static unsigned long vpci_major = 1;
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static unsigned long vpci_minor = 1;
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#define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
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struct iommu_batch {
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struct device *dev; /* Device mapping is for. */
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unsigned long prot; /* IOMMU page protections */
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unsigned long entry; /* Index into IOTSB. */
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u64 *pglist; /* List of physical pages */
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unsigned long npages; /* Number of pages in list. */
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};
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static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
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static int iommu_batch_initialized;
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/* Interrupts must be disabled. */
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static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
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{
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struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
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p->dev = dev;
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p->prot = prot;
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p->entry = entry;
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p->npages = 0;
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}
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/* Interrupts must be disabled. */
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static long iommu_batch_flush(struct iommu_batch *p)
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{
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struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
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unsigned long devhandle = pbm->devhandle;
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unsigned long prot = p->prot;
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unsigned long entry = p->entry;
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u64 *pglist = p->pglist;
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unsigned long npages = p->npages;
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while (npages != 0) {
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long num;
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num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
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npages, prot, __pa(pglist));
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if (unlikely(num < 0)) {
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if (printk_ratelimit())
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printk("iommu_batch_flush: IOMMU map of "
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"[%08lx:%08llx:%lx:%lx:%lx] failed with "
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"status %ld\n",
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devhandle, HV_PCI_TSBID(0, entry),
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npages, prot, __pa(pglist), num);
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return -1;
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}
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entry += num;
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npages -= num;
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pglist += num;
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}
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p->entry = entry;
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p->npages = 0;
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return 0;
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}
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static inline void iommu_batch_new_entry(unsigned long entry)
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{
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struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
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if (p->entry + p->npages == entry)
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return;
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if (p->entry != ~0UL)
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iommu_batch_flush(p);
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p->entry = entry;
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}
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/* Interrupts must be disabled. */
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static inline long iommu_batch_add(u64 phys_page)
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{
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struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
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BUG_ON(p->npages >= PGLIST_NENTS);
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p->pglist[p->npages++] = phys_page;
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if (p->npages == PGLIST_NENTS)
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return iommu_batch_flush(p);
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return 0;
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}
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/* Interrupts must be disabled. */
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static inline long iommu_batch_end(void)
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{
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struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
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BUG_ON(p->npages >= PGLIST_NENTS);
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return iommu_batch_flush(p);
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}
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static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addrp, gfp_t gfp,
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struct dma_attrs *attrs)
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{
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unsigned long flags, order, first_page, npages, n;
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struct iommu *iommu;
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struct page *page;
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void *ret;
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long entry;
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int nid;
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size = IO_PAGE_ALIGN(size);
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order = get_order(size);
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if (unlikely(order >= MAX_ORDER))
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return NULL;
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npages = size >> IO_PAGE_SHIFT;
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nid = dev->archdata.numa_node;
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page = alloc_pages_node(nid, gfp, order);
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if (unlikely(!page))
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return NULL;
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first_page = (unsigned long) page_address(page);
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memset((char *)first_page, 0, PAGE_SIZE << order);
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iommu = dev->archdata.iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = iommu_range_alloc(dev, iommu, npages, NULL);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry == DMA_ERROR_CODE))
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goto range_alloc_fail;
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*dma_addrp = (iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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first_page = __pa(first_page);
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local_irq_save(flags);
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iommu_batch_start(dev,
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(HV_PCI_MAP_ATTR_READ |
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HV_PCI_MAP_ATTR_WRITE),
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entry);
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for (n = 0; n < npages; n++) {
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long err = iommu_batch_add(first_page + (n * PAGE_SIZE));
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if (unlikely(err < 0L))
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goto iommu_map_fail;
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}
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if (unlikely(iommu_batch_end() < 0L))
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goto iommu_map_fail;
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local_irq_restore(flags);
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return ret;
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iommu_map_fail:
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/* Interrupts are disabled. */
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spin_lock(&iommu->lock);
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iommu_range_free(iommu, *dma_addrp, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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range_alloc_fail:
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free_pages(first_page, order);
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return NULL;
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}
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static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
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dma_addr_t dvma, struct dma_attrs *attrs)
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{
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struct pci_pbm_info *pbm;
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struct iommu *iommu;
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unsigned long flags, order, npages, entry;
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u32 devhandle;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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iommu = dev->archdata.iommu;
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pbm = dev->archdata.host_controller;
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devhandle = pbm->devhandle;
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entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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iommu_range_free(iommu, dvma, npages);
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do {
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unsigned long num;
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num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
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npages);
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entry += num;
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npages -= num;
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} while (npages != 0);
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spin_unlock_irqrestore(&iommu->lock, flags);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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}
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static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t sz,
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enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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struct iommu *iommu;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr;
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u32 bus_addr, ret;
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unsigned long prot;
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long entry;
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iommu = dev->archdata.iommu;
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if (unlikely(direction == DMA_NONE))
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goto bad;
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oaddr = (unsigned long)(page_address(page) + offset);
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = iommu_range_alloc(dev, iommu, npages, NULL);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry == DMA_ERROR_CODE))
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goto bad;
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bus_addr = (iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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prot = HV_PCI_MAP_ATTR_READ;
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if (direction != DMA_TO_DEVICE)
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prot |= HV_PCI_MAP_ATTR_WRITE;
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local_irq_save(flags);
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iommu_batch_start(dev, prot, entry);
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for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
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long err = iommu_batch_add(base_paddr);
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if (unlikely(err < 0L))
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goto iommu_map_fail;
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}
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if (unlikely(iommu_batch_end() < 0L))
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goto iommu_map_fail;
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local_irq_restore(flags);
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return ret;
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bad:
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if (printk_ratelimit())
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WARN_ON(1);
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return DMA_ERROR_CODE;
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iommu_map_fail:
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/* Interrupts are disabled. */
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spin_lock(&iommu->lock);
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iommu_range_free(iommu, bus_addr, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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return DMA_ERROR_CODE;
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}
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static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
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size_t sz, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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struct pci_pbm_info *pbm;
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struct iommu *iommu;
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unsigned long flags, npages;
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long entry;
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u32 devhandle;
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if (unlikely(direction == DMA_NONE)) {
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if (printk_ratelimit())
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WARN_ON(1);
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return;
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}
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iommu = dev->archdata.iommu;
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pbm = dev->archdata.host_controller;
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devhandle = pbm->devhandle;
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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iommu_range_free(iommu, bus_addr, npages);
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entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
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do {
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unsigned long num;
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num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
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npages);
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entry += num;
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npages -= num;
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} while (npages != 0);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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struct scatterlist *s, *outs, *segstart;
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unsigned long flags, handle, prot;
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dma_addr_t dma_next = 0, dma_addr;
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unsigned int max_seg_size;
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unsigned long seg_boundary_size;
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int outcount, incount, i;
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struct iommu *iommu;
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unsigned long base_shift;
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long err;
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BUG_ON(direction == DMA_NONE);
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iommu = dev->archdata.iommu;
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if (nelems == 0 || !iommu)
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return 0;
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prot = HV_PCI_MAP_ATTR_READ;
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if (direction != DMA_TO_DEVICE)
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prot |= HV_PCI_MAP_ATTR_WRITE;
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outs = s = segstart = &sglist[0];
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outcount = 1;
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incount = nelems;
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handle = 0;
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/* Init first segment length for backout at failure */
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outs->dma_length = 0;
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spin_lock_irqsave(&iommu->lock, flags);
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iommu_batch_start(dev, prot, ~0UL);
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max_seg_size = dma_get_max_seg_size(dev);
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seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
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IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
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base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
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for_each_sg(sglist, s, nelems, i) {
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unsigned long paddr, npages, entry, out_entry = 0, slen;
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slen = s->length;
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/* Sanity check */
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if (slen == 0) {
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dma_next = 0;
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continue;
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}
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/* Allocate iommu entries for that segment */
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paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
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npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
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entry = iommu_range_alloc(dev, iommu, npages, &handle);
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/* Handle failure */
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if (unlikely(entry == DMA_ERROR_CODE)) {
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if (printk_ratelimit())
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printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
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" npages %lx\n", iommu, paddr, npages);
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goto iommu_map_failed;
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}
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iommu_batch_new_entry(entry);
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/* Convert entry to a dma_addr_t */
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dma_addr = iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT);
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dma_addr |= (s->offset & ~IO_PAGE_MASK);
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/* Insert into HW table */
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paddr &= IO_PAGE_MASK;
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while (npages--) {
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err = iommu_batch_add(paddr);
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if (unlikely(err < 0L))
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goto iommu_map_failed;
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paddr += IO_PAGE_SIZE;
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}
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/* If we are in an open segment, try merging */
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if (segstart != s) {
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/* We cannot merge if:
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* - allocated dma_addr isn't contiguous to previous allocation
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*/
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if ((dma_addr != dma_next) ||
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(outs->dma_length + s->length > max_seg_size) ||
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(is_span_boundary(out_entry, base_shift,
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seg_boundary_size, outs, s))) {
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/* Can't merge: create a new segment */
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segstart = s;
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outcount++;
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outs = sg_next(outs);
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} else {
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outs->dma_length += s->length;
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}
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}
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if (segstart == s) {
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/* This is a new segment, fill entries */
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outs->dma_address = dma_addr;
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outs->dma_length = slen;
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out_entry = entry;
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}
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/* Calculate next page pointer for contiguous check */
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dma_next = dma_addr + slen;
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}
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err = iommu_batch_end();
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if (unlikely(err < 0L))
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goto iommu_map_failed;
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spin_unlock_irqrestore(&iommu->lock, flags);
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|
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if (outcount < incount) {
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outs = sg_next(outs);
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outs->dma_address = DMA_ERROR_CODE;
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outs->dma_length = 0;
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}
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return outcount;
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|
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iommu_map_failed:
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for_each_sg(sglist, s, nelems, i) {
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if (s->dma_length != 0) {
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unsigned long vaddr, npages;
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|
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vaddr = s->dma_address & IO_PAGE_MASK;
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npages = iommu_num_pages(s->dma_address, s->dma_length,
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IO_PAGE_SIZE);
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iommu_range_free(iommu, vaddr, npages);
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/* XXX demap? XXX */
|
|
s->dma_address = DMA_ERROR_CODE;
|
|
s->dma_length = 0;
|
|
}
|
|
if (s == outs)
|
|
break;
|
|
}
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
|
int nelems, enum dma_data_direction direction,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
struct pci_pbm_info *pbm;
|
|
struct scatterlist *sg;
|
|
struct iommu *iommu;
|
|
unsigned long flags;
|
|
u32 devhandle;
|
|
|
|
BUG_ON(direction == DMA_NONE);
|
|
|
|
iommu = dev->archdata.iommu;
|
|
pbm = dev->archdata.host_controller;
|
|
devhandle = pbm->devhandle;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
sg = sglist;
|
|
while (nelems--) {
|
|
dma_addr_t dma_handle = sg->dma_address;
|
|
unsigned int len = sg->dma_length;
|
|
unsigned long npages, entry;
|
|
|
|
if (!len)
|
|
break;
|
|
npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
|
|
iommu_range_free(iommu, dma_handle, npages);
|
|
|
|
entry = ((dma_handle - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
|
while (npages) {
|
|
unsigned long num;
|
|
|
|
num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
|
|
npages);
|
|
entry += num;
|
|
npages -= num;
|
|
}
|
|
|
|
sg = sg_next(sg);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static struct dma_map_ops sun4v_dma_ops = {
|
|
.alloc = dma_4v_alloc_coherent,
|
|
.free = dma_4v_free_coherent,
|
|
.map_page = dma_4v_map_page,
|
|
.unmap_page = dma_4v_unmap_page,
|
|
.map_sg = dma_4v_map_sg,
|
|
.unmap_sg = dma_4v_unmap_sg,
|
|
};
|
|
|
|
static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
|
|
{
|
|
struct property *prop;
|
|
struct device_node *dp;
|
|
|
|
dp = pbm->op->dev.of_node;
|
|
prop = of_find_property(dp, "66mhz-capable", NULL);
|
|
pbm->is_66mhz_capable = (prop != NULL);
|
|
pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
|
|
|
|
/* XXX register error interrupt handlers XXX */
|
|
}
|
|
|
|
static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
|
|
struct iommu *iommu)
|
|
{
|
|
struct iommu_arena *arena = &iommu->arena;
|
|
unsigned long i, cnt = 0;
|
|
u32 devhandle;
|
|
|
|
devhandle = pbm->devhandle;
|
|
for (i = 0; i < arena->limit; i++) {
|
|
unsigned long ret, io_attrs, ra;
|
|
|
|
ret = pci_sun4v_iommu_getmap(devhandle,
|
|
HV_PCI_TSBID(0, i),
|
|
&io_attrs, &ra);
|
|
if (ret == HV_EOK) {
|
|
if (page_in_phys_avail(ra)) {
|
|
pci_sun4v_iommu_demap(devhandle,
|
|
HV_PCI_TSBID(0, i), 1);
|
|
} else {
|
|
cnt++;
|
|
__set_bit(i, arena->map);
|
|
}
|
|
}
|
|
}
|
|
|
|
return cnt;
|
|
}
|
|
|
|
static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
|
|
{
|
|
static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
|
|
struct iommu *iommu = pbm->iommu;
|
|
unsigned long num_tsb_entries, sz;
|
|
u32 dma_mask, dma_offset;
|
|
const u32 *vdma;
|
|
|
|
vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
|
|
if (!vdma)
|
|
vdma = vdma_default;
|
|
|
|
if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
|
|
printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
|
|
vdma[0], vdma[1]);
|
|
return -EINVAL;
|
|
}
|
|
|
|
dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
|
|
num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
|
|
|
|
dma_offset = vdma[0];
|
|
|
|
/* Setup initial software IOMMU state. */
|
|
spin_lock_init(&iommu->lock);
|
|
iommu->ctx_lowest_free = 1;
|
|
iommu->page_table_map_base = dma_offset;
|
|
iommu->dma_addr_mask = dma_mask;
|
|
|
|
/* Allocate and initialize the free area map. */
|
|
sz = (num_tsb_entries + 7) / 8;
|
|
sz = (sz + 7UL) & ~7UL;
|
|
iommu->arena.map = kzalloc(sz, GFP_KERNEL);
|
|
if (!iommu->arena.map) {
|
|
printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
|
|
return -ENOMEM;
|
|
}
|
|
iommu->arena.limit = num_tsb_entries;
|
|
|
|
sz = probe_existing_entries(pbm, iommu);
|
|
if (sz)
|
|
printk("%s: Imported %lu TSB entries from OBP\n",
|
|
pbm->name, sz);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
struct pci_sun4v_msiq_entry {
|
|
u64 version_type;
|
|
#define MSIQ_VERSION_MASK 0xffffffff00000000UL
|
|
#define MSIQ_VERSION_SHIFT 32
|
|
#define MSIQ_TYPE_MASK 0x00000000000000ffUL
|
|
#define MSIQ_TYPE_SHIFT 0
|
|
#define MSIQ_TYPE_NONE 0x00
|
|
#define MSIQ_TYPE_MSG 0x01
|
|
#define MSIQ_TYPE_MSI32 0x02
|
|
#define MSIQ_TYPE_MSI64 0x03
|
|
#define MSIQ_TYPE_INTX 0x08
|
|
#define MSIQ_TYPE_NONE2 0xff
|
|
|
|
u64 intx_sysino;
|
|
u64 reserved1;
|
|
u64 stick;
|
|
u64 req_id; /* bus/device/func */
|
|
#define MSIQ_REQID_BUS_MASK 0xff00UL
|
|
#define MSIQ_REQID_BUS_SHIFT 8
|
|
#define MSIQ_REQID_DEVICE_MASK 0x00f8UL
|
|
#define MSIQ_REQID_DEVICE_SHIFT 3
|
|
#define MSIQ_REQID_FUNC_MASK 0x0007UL
|
|
#define MSIQ_REQID_FUNC_SHIFT 0
|
|
|
|
u64 msi_address;
|
|
|
|
/* The format of this value is message type dependent.
|
|
* For MSI bits 15:0 are the data from the MSI packet.
|
|
* For MSI-X bits 31:0 are the data from the MSI packet.
|
|
* For MSG, the message code and message routing code where:
|
|
* bits 39:32 is the bus/device/fn of the msg target-id
|
|
* bits 18:16 is the message routing code
|
|
* bits 7:0 is the message code
|
|
* For INTx the low order 2-bits are:
|
|
* 00 - INTA
|
|
* 01 - INTB
|
|
* 10 - INTC
|
|
* 11 - INTD
|
|
*/
|
|
u64 msi_data;
|
|
|
|
u64 reserved2;
|
|
};
|
|
|
|
static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
|
|
unsigned long *head)
|
|
{
|
|
unsigned long err, limit;
|
|
|
|
err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
|
|
if (unlikely(err))
|
|
return -ENXIO;
|
|
|
|
limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
|
|
if (unlikely(*head >= limit))
|
|
return -EFBIG;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
|
|
unsigned long msiqid, unsigned long *head,
|
|
unsigned long *msi)
|
|
{
|
|
struct pci_sun4v_msiq_entry *ep;
|
|
unsigned long err, type;
|
|
|
|
/* Note: void pointer arithmetic, 'head' is a byte offset */
|
|
ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
|
|
(pbm->msiq_ent_count *
|
|
sizeof(struct pci_sun4v_msiq_entry))) +
|
|
*head);
|
|
|
|
if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
|
|
return 0;
|
|
|
|
type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
|
|
if (unlikely(type != MSIQ_TYPE_MSI32 &&
|
|
type != MSIQ_TYPE_MSI64))
|
|
return -EINVAL;
|
|
|
|
*msi = ep->msi_data;
|
|
|
|
err = pci_sun4v_msi_setstate(pbm->devhandle,
|
|
ep->msi_data /* msi_num */,
|
|
HV_MSISTATE_IDLE);
|
|
if (unlikely(err))
|
|
return -ENXIO;
|
|
|
|
/* Clear the entry. */
|
|
ep->version_type &= ~MSIQ_TYPE_MASK;
|
|
|
|
(*head) += sizeof(struct pci_sun4v_msiq_entry);
|
|
if (*head >=
|
|
(pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
|
|
*head = 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
|
|
unsigned long head)
|
|
{
|
|
unsigned long err;
|
|
|
|
err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
|
|
if (unlikely(err))
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
|
|
unsigned long msi, int is_msi64)
|
|
{
|
|
if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
|
|
(is_msi64 ?
|
|
HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
|
|
return -ENXIO;
|
|
if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
|
|
return -ENXIO;
|
|
if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
|
|
return -ENXIO;
|
|
return 0;
|
|
}
|
|
|
|
static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
|
|
{
|
|
unsigned long err, msiqid;
|
|
|
|
err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
|
|
if (err)
|
|
return -ENXIO;
|
|
|
|
pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
|
|
{
|
|
unsigned long q_size, alloc_size, pages, order;
|
|
int i;
|
|
|
|
q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
|
|
alloc_size = (pbm->msiq_num * q_size);
|
|
order = get_order(alloc_size);
|
|
pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
|
|
if (pages == 0UL) {
|
|
printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
|
|
order);
|
|
return -ENOMEM;
|
|
}
|
|
memset((char *)pages, 0, PAGE_SIZE << order);
|
|
pbm->msi_queues = (void *) pages;
|
|
|
|
for (i = 0; i < pbm->msiq_num; i++) {
|
|
unsigned long err, base = __pa(pages + (i * q_size));
|
|
unsigned long ret1, ret2;
|
|
|
|
err = pci_sun4v_msiq_conf(pbm->devhandle,
|
|
pbm->msiq_first + i,
|
|
base, pbm->msiq_ent_count);
|
|
if (err) {
|
|
printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
|
|
err);
|
|
goto h_error;
|
|
}
|
|
|
|
err = pci_sun4v_msiq_info(pbm->devhandle,
|
|
pbm->msiq_first + i,
|
|
&ret1, &ret2);
|
|
if (err) {
|
|
printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
|
|
err);
|
|
goto h_error;
|
|
}
|
|
if (ret1 != base || ret2 != pbm->msiq_ent_count) {
|
|
printk(KERN_ERR "MSI: Bogus qconf "
|
|
"expected[%lx:%x] got[%lx:%lx]\n",
|
|
base, pbm->msiq_ent_count,
|
|
ret1, ret2);
|
|
goto h_error;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
h_error:
|
|
free_pages(pages, order);
|
|
return -EINVAL;
|
|
}
|
|
|
|
static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
|
|
{
|
|
unsigned long q_size, alloc_size, pages, order;
|
|
int i;
|
|
|
|
for (i = 0; i < pbm->msiq_num; i++) {
|
|
unsigned long msiqid = pbm->msiq_first + i;
|
|
|
|
(void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
|
|
}
|
|
|
|
q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
|
|
alloc_size = (pbm->msiq_num * q_size);
|
|
order = get_order(alloc_size);
|
|
|
|
pages = (unsigned long) pbm->msi_queues;
|
|
|
|
free_pages(pages, order);
|
|
|
|
pbm->msi_queues = NULL;
|
|
}
|
|
|
|
static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
|
|
unsigned long msiqid,
|
|
unsigned long devino)
|
|
{
|
|
unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
|
|
|
|
if (!irq)
|
|
return -ENOMEM;
|
|
|
|
if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
|
|
return -EINVAL;
|
|
if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
|
|
return -EINVAL;
|
|
|
|
return irq;
|
|
}
|
|
|
|
static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
|
|
.get_head = pci_sun4v_get_head,
|
|
.dequeue_msi = pci_sun4v_dequeue_msi,
|
|
.set_head = pci_sun4v_set_head,
|
|
.msi_setup = pci_sun4v_msi_setup,
|
|
.msi_teardown = pci_sun4v_msi_teardown,
|
|
.msiq_alloc = pci_sun4v_msiq_alloc,
|
|
.msiq_free = pci_sun4v_msiq_free,
|
|
.msiq_build_irq = pci_sun4v_msiq_build_irq,
|
|
};
|
|
|
|
static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
|
|
{
|
|
sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
|
|
}
|
|
#else /* CONFIG_PCI_MSI */
|
|
static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
|
|
{
|
|
}
|
|
#endif /* !(CONFIG_PCI_MSI) */
|
|
|
|
static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
|
|
struct platform_device *op, u32 devhandle)
|
|
{
|
|
struct device_node *dp = op->dev.of_node;
|
|
int err;
|
|
|
|
pbm->numa_node = of_node_to_nid(dp);
|
|
|
|
pbm->pci_ops = &sun4v_pci_ops;
|
|
pbm->config_space_reg_bits = 12;
|
|
|
|
pbm->index = pci_num_pbms++;
|
|
|
|
pbm->op = op;
|
|
|
|
pbm->devhandle = devhandle;
|
|
|
|
pbm->name = dp->full_name;
|
|
|
|
printk("%s: SUN4V PCI Bus Module\n", pbm->name);
|
|
printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
|
|
|
|
pci_determine_mem_io_space(pbm);
|
|
|
|
pci_get_pbm_props(pbm);
|
|
|
|
err = pci_sun4v_iommu_init(pbm);
|
|
if (err)
|
|
return err;
|
|
|
|
pci_sun4v_msi_init(pbm);
|
|
|
|
pci_sun4v_scan_bus(pbm, &op->dev);
|
|
|
|
pbm->next = pci_pbm_root;
|
|
pci_pbm_root = pbm;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pci_sun4v_probe(struct platform_device *op)
|
|
{
|
|
const struct linux_prom64_registers *regs;
|
|
static int hvapi_negotiated = 0;
|
|
struct pci_pbm_info *pbm;
|
|
struct device_node *dp;
|
|
struct iommu *iommu;
|
|
u32 devhandle;
|
|
int i, err;
|
|
|
|
dp = op->dev.of_node;
|
|
|
|
if (!hvapi_negotiated++) {
|
|
err = sun4v_hvapi_register(HV_GRP_PCI,
|
|
vpci_major,
|
|
&vpci_minor);
|
|
|
|
if (err) {
|
|
printk(KERN_ERR PFX "Could not register hvapi, "
|
|
"err=%d\n", err);
|
|
return err;
|
|
}
|
|
printk(KERN_INFO PFX "Registered hvapi major[%lu] minor[%lu]\n",
|
|
vpci_major, vpci_minor);
|
|
|
|
dma_ops = &sun4v_dma_ops;
|
|
}
|
|
|
|
regs = of_get_property(dp, "reg", NULL);
|
|
err = -ENODEV;
|
|
if (!regs) {
|
|
printk(KERN_ERR PFX "Could not find config registers\n");
|
|
goto out_err;
|
|
}
|
|
devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
|
|
|
|
err = -ENOMEM;
|
|
if (!iommu_batch_initialized) {
|
|
for_each_possible_cpu(i) {
|
|
unsigned long page = get_zeroed_page(GFP_KERNEL);
|
|
|
|
if (!page)
|
|
goto out_err;
|
|
|
|
per_cpu(iommu_batch, i).pglist = (u64 *) page;
|
|
}
|
|
iommu_batch_initialized = 1;
|
|
}
|
|
|
|
pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
|
|
if (!pbm) {
|
|
printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
|
|
goto out_err;
|
|
}
|
|
|
|
iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
|
|
if (!iommu) {
|
|
printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
|
|
goto out_free_controller;
|
|
}
|
|
|
|
pbm->iommu = iommu;
|
|
|
|
err = pci_sun4v_pbm_init(pbm, op, devhandle);
|
|
if (err)
|
|
goto out_free_iommu;
|
|
|
|
dev_set_drvdata(&op->dev, pbm);
|
|
|
|
return 0;
|
|
|
|
out_free_iommu:
|
|
kfree(pbm->iommu);
|
|
|
|
out_free_controller:
|
|
kfree(pbm);
|
|
|
|
out_err:
|
|
return err;
|
|
}
|
|
|
|
static const struct of_device_id pci_sun4v_match[] = {
|
|
{
|
|
.name = "pci",
|
|
.compatible = "SUNW,sun4v-pci",
|
|
},
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver pci_sun4v_driver = {
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = pci_sun4v_match,
|
|
},
|
|
.probe = pci_sun4v_probe,
|
|
};
|
|
|
|
static int __init pci_sun4v_init(void)
|
|
{
|
|
return platform_driver_register(&pci_sun4v_driver);
|
|
}
|
|
|
|
subsys_initcall(pci_sun4v_init);
|