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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
87 lines
2.0 KiB
Plaintext
87 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC8572DS Device Tree Source (36-bit address map)
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*
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* Copyright 2007-2009 Freescale Semiconductor Inc.
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*/
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/include/ "mpc8572si-pre.dtsi"
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/ {
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model = "fsl,MPC8572DS";
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compatible = "fsl,MPC8572DS";
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memory {
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device_type = "memory";
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};
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board_lbc: lbc: localbus@fffe05000 {
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reg = <0xf 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
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0x1 0x0 0xf 0xe0000000 0x08000000
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0x2 0x0 0xf 0xffa00000 0x00040000
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0x3 0x0 0xf 0xffdf0000 0x00008000
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0x4 0x0 0xf 0xffa40000 0x00040000
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0x5 0x0 0xf 0xffa80000 0x00040000
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0x6 0x0 0xf 0xffac0000 0x00040000>;
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};
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board_soc: soc: soc8572@fffe00000 {
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ranges = <0x0 0xf 0xffe00000 0x100000>;
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};
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board_pci0: pci0: pcie@fffe08000 {
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reg = <0xf 0xffe08000 0 0x1000>;
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ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci1: pcie@fffe09000 {
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reg = <0xf 0xffe09000 0 0x1000>;
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ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci2: pcie@fffe0a000 {
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reg = <0xf 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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};
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/*
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* mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
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* for interrupt-map & interrupt-map-mask
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*/
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/include/ "mpc8572si-post.dtsi"
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/include/ "mpc8572ds.dtsi"
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