mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4e530fba69
Avoid excessive scheduling delays under a preemptible kernel by yielding the NEON after every block of input. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
288 lines
7.0 KiB
ArmAsm
288 lines
7.0 KiB
ArmAsm
/*
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* Accelerated CRC32(C) using arm64 CRC, NEON and Crypto Extensions instructions
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*
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* Copyright (C) 2016 Linaro Ltd <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* GPL HEADER START
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*
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 only,
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License version 2 for more details (a copy is included
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* in the LICENSE file that accompanied this code).
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*
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* You should have received a copy of the GNU General Public License
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* version 2 along with this program; If not, see http://www.gnu.org/licenses
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*
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* Please visit http://www.xyratex.com/contact if you need additional
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* information or have any questions.
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*
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* GPL HEADER END
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*/
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/*
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* Copyright 2012 Xyratex Technology Limited
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*
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* Using hardware provided PCLMULQDQ instruction to accelerate the CRC32
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* calculation.
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* CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE)
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* PCLMULQDQ is a new instruction in Intel SSE4.2, the reference can be found
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* at:
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* http://www.intel.com/products/processor/manuals/
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* Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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* Volume 2B: Instruction Set Reference, N-Z
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*
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* Authors: Gregory Prestas <Gregory_Prestas@us.xyratex.com>
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* Alexander Boyko <Alexander_Boyko@xyratex.com>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.section ".rodata", "a"
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.align 6
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.cpu generic+crypto+crc
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.Lcrc32_constants:
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/*
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* [x4*128+32 mod P(x) << 32)]' << 1 = 0x154442bd4
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* #define CONSTANT_R1 0x154442bd4LL
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*
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* [(x4*128-32 mod P(x) << 32)]' << 1 = 0x1c6e41596
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* #define CONSTANT_R2 0x1c6e41596LL
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*/
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.octa 0x00000001c6e415960000000154442bd4
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/*
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* [(x128+32 mod P(x) << 32)]' << 1 = 0x1751997d0
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* #define CONSTANT_R3 0x1751997d0LL
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*
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* [(x128-32 mod P(x) << 32)]' << 1 = 0x0ccaa009e
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* #define CONSTANT_R4 0x0ccaa009eLL
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*/
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.octa 0x00000000ccaa009e00000001751997d0
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/*
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* [(x64 mod P(x) << 32)]' << 1 = 0x163cd6124
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* #define CONSTANT_R5 0x163cd6124LL
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*/
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.quad 0x0000000163cd6124
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.quad 0x00000000FFFFFFFF
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/*
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* #define CRCPOLY_TRUE_LE_FULL 0x1DB710641LL
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*
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* Barrett Reduction constant (u64`) = u` = (x**64 / P(x))`
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* = 0x1F7011641LL
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* #define CONSTANT_RU 0x1F7011641LL
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*/
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.octa 0x00000001F701164100000001DB710641
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.Lcrc32c_constants:
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.octa 0x000000009e4addf800000000740eef02
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.octa 0x000000014cd00bd600000000f20c0dfe
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.quad 0x00000000dd45aab8
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.quad 0x00000000FFFFFFFF
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.octa 0x00000000dea713f10000000105ec76f0
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vCONSTANT .req v0
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dCONSTANT .req d0
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qCONSTANT .req q0
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BUF .req x19
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LEN .req x20
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CRC .req x21
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CONST .req x22
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vzr .req v9
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/**
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* Calculate crc32
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* BUF - buffer
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* LEN - sizeof buffer (multiple of 16 bytes), LEN should be > 63
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* CRC - initial crc32
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* return %eax crc32
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* uint crc32_pmull_le(unsigned char const *buffer,
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* size_t len, uint crc32)
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*/
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.text
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ENTRY(crc32_pmull_le)
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adr_l x3, .Lcrc32_constants
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b 0f
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ENTRY(crc32c_pmull_le)
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adr_l x3, .Lcrc32c_constants
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0: frame_push 4, 64
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mov BUF, x0
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mov LEN, x1
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mov CRC, x2
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mov CONST, x3
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bic LEN, LEN, #15
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ld1 {v1.16b-v4.16b}, [BUF], #0x40
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movi vzr.16b, #0
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fmov dCONSTANT, CRC
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eor v1.16b, v1.16b, vCONSTANT.16b
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sub LEN, LEN, #0x40
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cmp LEN, #0x40
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b.lt less_64
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ldr qCONSTANT, [CONST]
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loop_64: /* 64 bytes Full cache line folding */
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sub LEN, LEN, #0x40
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pmull2 v5.1q, v1.2d, vCONSTANT.2d
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pmull2 v6.1q, v2.2d, vCONSTANT.2d
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pmull2 v7.1q, v3.2d, vCONSTANT.2d
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pmull2 v8.1q, v4.2d, vCONSTANT.2d
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pmull v1.1q, v1.1d, vCONSTANT.1d
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pmull v2.1q, v2.1d, vCONSTANT.1d
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pmull v3.1q, v3.1d, vCONSTANT.1d
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pmull v4.1q, v4.1d, vCONSTANT.1d
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eor v1.16b, v1.16b, v5.16b
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ld1 {v5.16b}, [BUF], #0x10
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eor v2.16b, v2.16b, v6.16b
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ld1 {v6.16b}, [BUF], #0x10
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eor v3.16b, v3.16b, v7.16b
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ld1 {v7.16b}, [BUF], #0x10
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eor v4.16b, v4.16b, v8.16b
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ld1 {v8.16b}, [BUF], #0x10
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eor v1.16b, v1.16b, v5.16b
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eor v2.16b, v2.16b, v6.16b
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eor v3.16b, v3.16b, v7.16b
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eor v4.16b, v4.16b, v8.16b
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cmp LEN, #0x40
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b.lt less_64
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if_will_cond_yield_neon
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stp q1, q2, [sp, #.Lframe_local_offset]
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stp q3, q4, [sp, #.Lframe_local_offset + 32]
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do_cond_yield_neon
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ldp q1, q2, [sp, #.Lframe_local_offset]
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ldp q3, q4, [sp, #.Lframe_local_offset + 32]
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ldr qCONSTANT, [CONST]
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movi vzr.16b, #0
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endif_yield_neon
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b loop_64
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less_64: /* Folding cache line into 128bit */
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ldr qCONSTANT, [CONST, #16]
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pmull2 v5.1q, v1.2d, vCONSTANT.2d
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pmull v1.1q, v1.1d, vCONSTANT.1d
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eor v1.16b, v1.16b, v5.16b
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eor v1.16b, v1.16b, v2.16b
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pmull2 v5.1q, v1.2d, vCONSTANT.2d
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pmull v1.1q, v1.1d, vCONSTANT.1d
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eor v1.16b, v1.16b, v5.16b
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eor v1.16b, v1.16b, v3.16b
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pmull2 v5.1q, v1.2d, vCONSTANT.2d
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pmull v1.1q, v1.1d, vCONSTANT.1d
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eor v1.16b, v1.16b, v5.16b
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eor v1.16b, v1.16b, v4.16b
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cbz LEN, fold_64
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loop_16: /* Folding rest buffer into 128bit */
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subs LEN, LEN, #0x10
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ld1 {v2.16b}, [BUF], #0x10
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pmull2 v5.1q, v1.2d, vCONSTANT.2d
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pmull v1.1q, v1.1d, vCONSTANT.1d
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eor v1.16b, v1.16b, v5.16b
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eor v1.16b, v1.16b, v2.16b
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b.ne loop_16
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fold_64:
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/* perform the last 64 bit fold, also adds 32 zeroes
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* to the input stream */
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ext v2.16b, v1.16b, v1.16b, #8
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pmull2 v2.1q, v2.2d, vCONSTANT.2d
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ext v1.16b, v1.16b, vzr.16b, #8
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eor v1.16b, v1.16b, v2.16b
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/* final 32-bit fold */
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ldr dCONSTANT, [CONST, #32]
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ldr d3, [CONST, #40]
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ext v2.16b, v1.16b, vzr.16b, #4
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and v1.16b, v1.16b, v3.16b
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pmull v1.1q, v1.1d, vCONSTANT.1d
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eor v1.16b, v1.16b, v2.16b
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/* Finish up with the bit-reversed barrett reduction 64 ==> 32 bits */
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ldr qCONSTANT, [CONST, #48]
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and v2.16b, v1.16b, v3.16b
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ext v2.16b, vzr.16b, v2.16b, #8
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pmull2 v2.1q, v2.2d, vCONSTANT.2d
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and v2.16b, v2.16b, v3.16b
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pmull v2.1q, v2.1d, vCONSTANT.1d
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eor v1.16b, v1.16b, v2.16b
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mov w0, v1.s[1]
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frame_pop
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ret
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ENDPROC(crc32_pmull_le)
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ENDPROC(crc32c_pmull_le)
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.macro __crc32, c
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0: subs x2, x2, #16
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b.mi 8f
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ldp x3, x4, [x1], #16
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CPU_BE( rev x3, x3 )
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CPU_BE( rev x4, x4 )
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crc32\c\()x w0, w0, x3
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crc32\c\()x w0, w0, x4
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b.ne 0b
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ret
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8: tbz x2, #3, 4f
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ldr x3, [x1], #8
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CPU_BE( rev x3, x3 )
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crc32\c\()x w0, w0, x3
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4: tbz x2, #2, 2f
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ldr w3, [x1], #4
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CPU_BE( rev w3, w3 )
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crc32\c\()w w0, w0, w3
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2: tbz x2, #1, 1f
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ldrh w3, [x1], #2
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CPU_BE( rev16 w3, w3 )
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crc32\c\()h w0, w0, w3
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1: tbz x2, #0, 0f
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ldrb w3, [x1]
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crc32\c\()b w0, w0, w3
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0: ret
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.endm
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.align 5
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ENTRY(crc32_armv8_le)
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__crc32
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ENDPROC(crc32_armv8_le)
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.align 5
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ENTRY(crc32c_armv8_le)
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__crc32 c
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ENDPROC(crc32c_armv8_le)
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