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48d823878d
Allocate and populate the default LRC for every ring, call gen-specific init/cleanup, init/fini the command parser and set the status page (now inside the LRC object). These are things all engines/rings have in common. Stopping the ring before cleanup and initializing the seqnos is left as a TODO task (we need more infrastructure in place before we can achieve this). v2: Check the ringbuffer backing obj for ring_is_initialized, instead of the context backing obj (similar, but not exactly the same). Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
517 lines
15 KiB
C
517 lines
15 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Ben Widawsky <ben@bwidawsk.net>
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* Michel Thierry <michel.thierry@intel.com>
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* Thomas Daniel <thomas.daniel@intel.com>
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* Oscar Mateo <oscar.mateo@intel.com>
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*
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*/
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/*
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* GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
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* These expanded contexts enable a number of new abilities, especially
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* "Execlists" (also implemented in this file).
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*
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* Execlists are the new method by which, on gen8+ hardware, workloads are
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* submitted for execution (as opposed to the legacy, ringbuffer-based, method).
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*/
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_ALIGN 4096
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#define RING_ELSP(ring) ((ring)->mmio_base+0x230)
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#define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
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#define CTX_LRI_HEADER_0 0x01
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#define CTX_CONTEXT_CONTROL 0x02
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#define CTX_RING_HEAD 0x04
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#define CTX_RING_TAIL 0x06
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#define CTX_RING_BUFFER_START 0x08
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#define CTX_RING_BUFFER_CONTROL 0x0a
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#define CTX_BB_HEAD_U 0x0c
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#define CTX_BB_HEAD_L 0x0e
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#define CTX_BB_STATE 0x10
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#define CTX_SECOND_BB_HEAD_U 0x12
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#define CTX_SECOND_BB_HEAD_L 0x14
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#define CTX_SECOND_BB_STATE 0x16
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#define CTX_BB_PER_CTX_PTR 0x18
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#define CTX_RCS_INDIRECT_CTX 0x1a
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#define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
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#define CTX_LRI_HEADER_1 0x21
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#define CTX_CTX_TIMESTAMP 0x22
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#define CTX_PDP3_UDW 0x24
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#define CTX_PDP3_LDW 0x26
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#define CTX_PDP2_UDW 0x28
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#define CTX_PDP2_LDW 0x2a
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#define CTX_PDP1_UDW 0x2c
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#define CTX_PDP1_LDW 0x2e
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#define CTX_PDP0_UDW 0x30
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#define CTX_PDP0_LDW 0x32
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#define CTX_LRI_HEADER_2 0x41
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#define CTX_R_PWR_CLK_STATE 0x42
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#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
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{
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WARN_ON(i915.enable_ppgtt == -1);
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if (enable_execlists == 0)
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return 0;
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if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev))
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return 1;
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return 0;
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}
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int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
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struct intel_engine_cs *ring,
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struct intel_context *ctx,
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struct drm_i915_gem_execbuffer2 *args,
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struct list_head *vmas,
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struct drm_i915_gem_object *batch_obj,
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u64 exec_start, u32 flags)
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{
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/* TODO */
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return 0;
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}
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void intel_logical_ring_stop(struct intel_engine_cs *ring)
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{
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/* TODO */
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}
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void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
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{
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if (!intel_ring_initialized(ring))
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return;
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/* TODO: make sure the ring is stopped */
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ring->preallocated_lazy_request = NULL;
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ring->outstanding_lazy_seqno = 0;
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if (ring->cleanup)
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ring->cleanup(ring);
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i915_cmd_parser_fini_ring(ring);
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if (ring->status_page.obj) {
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kunmap(sg_page(ring->status_page.obj->pages->sgl));
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ring->status_page.obj = NULL;
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}
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}
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static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
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{
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int ret;
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struct intel_context *dctx = ring->default_context;
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struct drm_i915_gem_object *dctx_obj;
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/* Intentionally left blank. */
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ring->buffer = NULL;
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ring->dev = dev;
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INIT_LIST_HEAD(&ring->active_list);
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INIT_LIST_HEAD(&ring->request_list);
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init_waitqueue_head(&ring->irq_queue);
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ret = intel_lr_context_deferred_create(dctx, ring);
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if (ret)
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return ret;
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/* The status page is offset 0 from the context object in LRCs. */
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dctx_obj = dctx->engine[ring->id].state;
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ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj);
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ring->status_page.page_addr = kmap(sg_page(dctx_obj->pages->sgl));
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if (ring->status_page.page_addr == NULL)
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return -ENOMEM;
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ring->status_page.obj = dctx_obj;
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ret = i915_cmd_parser_init_ring(ring);
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if (ret)
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return ret;
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if (ring->init) {
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ret = ring->init(ring);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int logical_render_ring_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_engine_cs *ring = &dev_priv->ring[RCS];
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ring->name = "render ring";
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ring->id = RCS;
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ring->mmio_base = RENDER_RING_BASE;
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ring->irq_enable_mask =
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GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
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return logical_ring_init(dev, ring);
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}
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static int logical_bsd_ring_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_engine_cs *ring = &dev_priv->ring[VCS];
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ring->name = "bsd ring";
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ring->id = VCS;
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ring->mmio_base = GEN6_BSD_RING_BASE;
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ring->irq_enable_mask =
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GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
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return logical_ring_init(dev, ring);
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}
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static int logical_bsd2_ring_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
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ring->name = "bds2 ring";
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ring->id = VCS2;
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ring->mmio_base = GEN8_BSD2_RING_BASE;
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ring->irq_enable_mask =
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GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
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return logical_ring_init(dev, ring);
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}
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static int logical_blt_ring_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_engine_cs *ring = &dev_priv->ring[BCS];
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ring->name = "blitter ring";
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ring->id = BCS;
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ring->mmio_base = BLT_RING_BASE;
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ring->irq_enable_mask =
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GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
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return logical_ring_init(dev, ring);
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}
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static int logical_vebox_ring_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_engine_cs *ring = &dev_priv->ring[VECS];
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ring->name = "video enhancement ring";
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ring->id = VECS;
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ring->mmio_base = VEBOX_RING_BASE;
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ring->irq_enable_mask =
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GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
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return logical_ring_init(dev, ring);
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}
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int intel_logical_rings_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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ret = logical_render_ring_init(dev);
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if (ret)
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return ret;
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if (HAS_BSD(dev)) {
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ret = logical_bsd_ring_init(dev);
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if (ret)
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goto cleanup_render_ring;
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}
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if (HAS_BLT(dev)) {
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ret = logical_blt_ring_init(dev);
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if (ret)
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goto cleanup_bsd_ring;
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}
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if (HAS_VEBOX(dev)) {
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ret = logical_vebox_ring_init(dev);
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if (ret)
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goto cleanup_blt_ring;
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}
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if (HAS_BSD2(dev)) {
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ret = logical_bsd2_ring_init(dev);
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if (ret)
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goto cleanup_vebox_ring;
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}
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ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
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if (ret)
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goto cleanup_bsd2_ring;
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return 0;
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cleanup_bsd2_ring:
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intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
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cleanup_vebox_ring:
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intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
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cleanup_blt_ring:
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intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
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cleanup_bsd_ring:
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intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
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cleanup_render_ring:
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intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
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return ret;
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}
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static int
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populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
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struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
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{
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struct drm_i915_gem_object *ring_obj = ringbuf->obj;
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struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
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struct page *page;
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uint32_t *reg_state;
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int ret;
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ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
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if (ret) {
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DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
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return ret;
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}
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ret = i915_gem_object_get_pages(ctx_obj);
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if (ret) {
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DRM_DEBUG_DRIVER("Could not get object pages\n");
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return ret;
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}
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i915_gem_object_pin_pages(ctx_obj);
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/* The second page of the context object contains some fields which must
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* be set up prior to the first execution. */
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page = i915_gem_object_get_page(ctx_obj, 1);
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reg_state = kmap_atomic(page);
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/* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
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* commands followed by (reg, value) pairs. The values we are setting here are
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* only for the first context restore: on a subsequent save, the GPU will
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* recreate this batchbuffer with new values (including all the missing
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* MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
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if (ring->id == RCS)
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reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
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else
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reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
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reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
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reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
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reg_state[CTX_CONTEXT_CONTROL+1] =
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_MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
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reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
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reg_state[CTX_RING_HEAD+1] = 0;
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reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
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reg_state[CTX_RING_TAIL+1] = 0;
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reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
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reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
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reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
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reg_state[CTX_RING_BUFFER_CONTROL+1] =
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((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
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reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
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reg_state[CTX_BB_HEAD_U+1] = 0;
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reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
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reg_state[CTX_BB_HEAD_L+1] = 0;
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reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
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reg_state[CTX_BB_STATE+1] = (1<<5);
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reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
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reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
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reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
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reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
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reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
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reg_state[CTX_SECOND_BB_STATE+1] = 0;
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if (ring->id == RCS) {
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/* TODO: according to BSpec, the register state context
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* for CHV does not have these. OTOH, these registers do
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* exist in CHV. I'm waiting for a clarification */
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reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
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reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
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reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
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reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
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reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
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reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
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}
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reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
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reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
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reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
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reg_state[CTX_CTX_TIMESTAMP+1] = 0;
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reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
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reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
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reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
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reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
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reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
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reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
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reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
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reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
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reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
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reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
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reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
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reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
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reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
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reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
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reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
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reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
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if (ring->id == RCS) {
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reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
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reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
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reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
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}
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kunmap_atomic(reg_state);
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ctx_obj->dirty = 1;
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set_page_dirty(page);
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i915_gem_object_unpin_pages(ctx_obj);
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return 0;
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}
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void intel_lr_context_free(struct intel_context *ctx)
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{
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int i;
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for (i = 0; i < I915_NUM_RINGS; i++) {
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struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
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struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
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if (ctx_obj) {
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intel_destroy_ringbuffer_obj(ringbuf);
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kfree(ringbuf);
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i915_gem_object_ggtt_unpin(ctx_obj);
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drm_gem_object_unreference(&ctx_obj->base);
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}
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}
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}
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static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
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{
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int ret = 0;
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|
|
WARN_ON(INTEL_INFO(ring->dev)->gen != 8);
|
|
|
|
switch (ring->id) {
|
|
case RCS:
|
|
ret = GEN8_LR_CONTEXT_RENDER_SIZE;
|
|
break;
|
|
case VCS:
|
|
case BCS:
|
|
case VECS:
|
|
case VCS2:
|
|
ret = GEN8_LR_CONTEXT_OTHER_SIZE;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int intel_lr_context_deferred_create(struct intel_context *ctx,
|
|
struct intel_engine_cs *ring)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
|
struct drm_i915_gem_object *ctx_obj;
|
|
uint32_t context_size;
|
|
struct intel_ringbuffer *ringbuf;
|
|
int ret;
|
|
|
|
WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
|
|
if (ctx->engine[ring->id].state)
|
|
return 0;
|
|
|
|
context_size = round_up(get_lr_context_size(ring), 4096);
|
|
|
|
ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
|
|
if (IS_ERR(ctx_obj)) {
|
|
ret = PTR_ERR(ctx_obj);
|
|
DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
|
|
if (ret) {
|
|
DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret);
|
|
drm_gem_object_unreference(&ctx_obj->base);
|
|
return ret;
|
|
}
|
|
|
|
ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
|
|
if (!ringbuf) {
|
|
DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
|
|
ring->name);
|
|
i915_gem_object_ggtt_unpin(ctx_obj);
|
|
drm_gem_object_unreference(&ctx_obj->base);
|
|
ret = -ENOMEM;
|
|
return ret;
|
|
}
|
|
|
|
ringbuf->ring = ring;
|
|
ringbuf->size = 32 * PAGE_SIZE;
|
|
ringbuf->effective_size = ringbuf->size;
|
|
ringbuf->head = 0;
|
|
ringbuf->tail = 0;
|
|
ringbuf->space = ringbuf->size;
|
|
ringbuf->last_retired_head = -1;
|
|
|
|
/* TODO: For now we put this in the mappable region so that we can reuse
|
|
* the existing ringbuffer code which ioremaps it. When we start
|
|
* creating many contexts, this will no longer work and we must switch
|
|
* to a kmapish interface.
|
|
*/
|
|
ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
|
|
if (ret) {
|
|
DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n",
|
|
ring->name, ret);
|
|
goto error;
|
|
}
|
|
|
|
ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
|
|
if (ret) {
|
|
DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
|
|
intel_destroy_ringbuffer_obj(ringbuf);
|
|
goto error;
|
|
}
|
|
|
|
ctx->engine[ring->id].ringbuf = ringbuf;
|
|
ctx->engine[ring->id].state = ctx_obj;
|
|
|
|
return 0;
|
|
|
|
error:
|
|
kfree(ringbuf);
|
|
i915_gem_object_ggtt_unpin(ctx_obj);
|
|
drm_gem_object_unreference(&ctx_obj->base);
|
|
return ret;
|
|
}
|