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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f5523423de
Booting 5.4 on LX2160A reveals that KVM is non-functional:
kvm: Limiting the IPA size due to kernel Virtual Address limit
kvm [1]: IPA Size Limit: 43bits
kvm [1]: IDMAP intersecting with HYP VA, unable to continue
kvm [1]: error initializing Hyp mode: -22
Debugging shows:
kvm [1]: IDMAP page: 81a26000
kvm [1]: HYP VA range: 0:22ffffffff
as RAM is located at:
80000000-fbdfffff : System RAM
2080000000-237fffffff : System RAM
Comparing this with the same kernel on Armada 8040 shows:
kvm: Limiting the IPA size due to kernel Virtual Address limit
kvm [1]: IPA Size Limit: 43bits
kvm [1]: IDMAP page: 2a26000
kvm [1]: HYP VA range: 4800000000:493fffffff
...
kvm [1]: Hyp mode initialized successfully
which indicates that hyp_va_msb is set, and is always set to the
opposite value of the idmap page to avoid the overlap. This does not
happen with the LX2160A.
Further debugging shows vabits_actual = 39, kva_msb = 38 on LX2160A and
kva_msb = 33 on Armada 8040. Looking at the bit layout of the HYP VA,
there is still one bit available for hyp_va_msb. Set this bit
appropriately. This allows KVM to be functional on the LX2160A, but
without any HYP VA randomisation:
kvm: Limiting the IPA size due to kernel Virtual Address limit
kvm [1]: IPA Size Limit: 43bits
kvm [1]: IDMAP page: 81a24000
kvm [1]: HYP VA range: 4000000000:62ffffffff
...
kvm [1]: Hyp mode initialized successfully
Fixes: ed57cac83e
("arm64: KVM: Introduce EL2 VA randomisation")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
[maz: small additional cleanups, preserved case where the tag
is legitimately 0 and we can just use the mask, Fixes tag]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/E1ilAiY-0000MA-RG@rmk-PC.armlinux.org.uk
204 lines
5.1 KiB
C
204 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <linux/kvm_host.h>
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#include <linux/random.h>
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#include <linux/memblock.h>
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#include <asm/alternative.h>
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#include <asm/debug-monitors.h>
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#include <asm/insn.h>
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#include <asm/kvm_mmu.h>
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/*
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* The LSB of the HYP VA tag
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*/
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static u8 tag_lsb;
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/*
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* The HYP VA tag value with the region bit
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*/
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static u64 tag_val;
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static u64 va_mask;
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/*
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* We want to generate a hyp VA with the following format (with V ==
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* vabits_actual):
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*
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* 63 ... V | V-1 | V-2 .. tag_lsb | tag_lsb - 1 .. 0
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* ---------------------------------------------------------
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* | 0000000 | hyp_va_msb | random tag | kern linear VA |
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* |--------- tag_val -----------|----- va_mask ---|
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*
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* which does not conflict with the idmap regions.
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*/
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__init void kvm_compute_layout(void)
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{
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phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
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u64 hyp_va_msb;
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/* Where is my RAM region? */
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hyp_va_msb = idmap_addr & BIT(vabits_actual - 1);
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hyp_va_msb ^= BIT(vabits_actual - 1);
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tag_lsb = fls64((u64)phys_to_virt(memblock_start_of_DRAM()) ^
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(u64)(high_memory - 1));
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va_mask = GENMASK_ULL(tag_lsb - 1, 0);
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tag_val = hyp_va_msb;
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if (tag_lsb != (vabits_actual - 1)) {
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/* We have some free bits to insert a random tag. */
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tag_val |= get_random_long() & GENMASK_ULL(vabits_actual - 2, tag_lsb);
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}
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tag_val >>= tag_lsb;
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}
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static u32 compute_instruction(int n, u32 rd, u32 rn)
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{
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u32 insn = AARCH64_BREAK_FAULT;
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switch (n) {
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case 0:
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insn = aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_AND,
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AARCH64_INSN_VARIANT_64BIT,
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rn, rd, va_mask);
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break;
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case 1:
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/* ROR is a variant of EXTR with Rm = Rn */
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insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
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rn, rn, rd,
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tag_lsb);
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break;
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case 2:
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insn = aarch64_insn_gen_add_sub_imm(rd, rn,
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tag_val & GENMASK(11, 0),
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_ADSB_ADD);
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break;
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case 3:
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insn = aarch64_insn_gen_add_sub_imm(rd, rn,
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tag_val & GENMASK(23, 12),
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_ADSB_ADD);
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break;
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case 4:
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/* ROR is a variant of EXTR with Rm = Rn */
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insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
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rn, rn, rd, 64 - tag_lsb);
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break;
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}
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return insn;
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}
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void __init kvm_update_va_mask(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr, int nr_inst)
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{
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int i;
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BUG_ON(nr_inst != 5);
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for (i = 0; i < nr_inst; i++) {
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u32 rd, rn, insn, oinsn;
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/*
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* VHE doesn't need any address translation, let's NOP
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* everything.
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*
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* Alternatively, if the tag is zero (because the layout
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* dictates it and we don't have any spare bits in the
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* address), NOP everything after masking the kernel VA.
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*/
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if (has_vhe() || (!tag_val && i > 0)) {
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updptr[i] = cpu_to_le32(aarch64_insn_gen_nop());
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continue;
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}
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oinsn = le32_to_cpu(origptr[i]);
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rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
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rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn);
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insn = compute_instruction(i, rd, rn);
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BUG_ON(insn == AARCH64_BREAK_FAULT);
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updptr[i] = cpu_to_le32(insn);
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}
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}
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void *__kvm_bp_vect_base;
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int __kvm_harden_el2_vector_slot;
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void kvm_patch_vector_branch(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr, int nr_inst)
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{
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u64 addr;
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u32 insn;
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BUG_ON(nr_inst != 5);
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if (has_vhe() || !cpus_have_const_cap(ARM64_HARDEN_EL2_VECTORS)) {
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WARN_ON_ONCE(cpus_have_const_cap(ARM64_HARDEN_EL2_VECTORS));
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return;
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}
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/*
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* Compute HYP VA by using the same computation as kern_hyp_va()
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*/
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addr = (uintptr_t)kvm_ksym_ref(__kvm_hyp_vector);
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addr &= va_mask;
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addr |= tag_val << tag_lsb;
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/* Use PC[10:7] to branch to the same vector in KVM */
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addr |= ((u64)origptr & GENMASK_ULL(10, 7));
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/*
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* Branch over the preamble in order to avoid the initial store on
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* the stack (which we already perform in the hardening vectors).
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*/
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addr += KVM_VECTOR_PREAMBLE;
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/* stp x0, x1, [sp, #-16]! */
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insn = aarch64_insn_gen_load_store_pair(AARCH64_INSN_REG_0,
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AARCH64_INSN_REG_1,
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AARCH64_INSN_REG_SP,
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-16,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX);
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*updptr++ = cpu_to_le32(insn);
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/* movz x0, #(addr & 0xffff) */
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insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
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(u16)addr,
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0,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_ZERO);
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*updptr++ = cpu_to_le32(insn);
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/* movk x0, #((addr >> 16) & 0xffff), lsl #16 */
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insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
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(u16)(addr >> 16),
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16,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_KEEP);
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*updptr++ = cpu_to_le32(insn);
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/* movk x0, #((addr >> 32) & 0xffff), lsl #32 */
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insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
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(u16)(addr >> 32),
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32,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_KEEP);
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*updptr++ = cpu_to_le32(insn);
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/* br x0 */
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insn = aarch64_insn_gen_branch_reg(AARCH64_INSN_REG_0,
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AARCH64_INSN_BRANCH_NOLINK);
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*updptr++ = cpu_to_le32(insn);
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}
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