mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
0f3a05cb43
Now that Yosemite's gone we can move the MSP71xx code one level up. Shane McDonald <mcdonald.shane@gmail.com>'s https://patchwork.linux-mips.org/patch/4736/ has been folded into this patch. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
30 lines
933 B
C
30 lines
933 B
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
|
*/
|
|
#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
|
|
#define __ASM_MIPS_PMC_SIERRA_WAR_H
|
|
|
|
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
|
#define R4600_V1_HIT_CACHEOP_WAR 0
|
|
#define R4600_V2_HIT_CACHEOP_WAR 0
|
|
#define R5432_CP0_INTERRUPT_WAR 0
|
|
#define BCM1250_M3_WAR 0
|
|
#define SIBYTE_1956_WAR 0
|
|
#define MIPS4K_ICACHE_REFILL_WAR 0
|
|
#define MIPS_CACHE_SYNC_WAR 0
|
|
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
|
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
|
#define R10000_LLSC_WAR 0
|
|
#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
|
|
defined(CONFIG_PMC_MSP7120_FPGA)
|
|
#define MIPS34K_MISSED_ITLB_WAR 1
|
|
#else
|
|
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
#endif
|
|
|
|
#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
|