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8d3d589a79
Some pseries IOMMUs cache TCEs but don't snoop when the TCEs are changed in memory, hence we need manually invalidate in software. This adds code to do the invalidate. It keys off a device tree property to say where the to do the MMIO for the invalidate and some information on what the format of the invalidate including some magic routing info. it_busno get overloaded with this magic routing info and it_index with the MMIO address for the invalidate command. This then gets hooked into the building and freeing of TCEs. This is only useful on bare metal pseries. pHyp takes care of this when virtualised. Based on patch from Milton with cleanups from Mikey. Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
53 lines
1.7 KiB
C
53 lines
1.7 KiB
C
/*
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
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* Rewrite, cleanup:
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_POWERPC_TCE_H
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#define _ASM_POWERPC_TCE_H
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#ifdef __KERNEL__
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#include <asm/iommu.h>
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/*
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* Tces come in two formats, one for the virtual bus and a different
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* format for PCI. PCI TCEs can have hardware or software maintianed
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* coherency.
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*/
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#define TCE_VB 0
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#define TCE_PCI 1
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#define TCE_PCI_SW_INVAL 2
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/* TCE page size is 4096 bytes (1 << 12) */
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#define TCE_SHIFT 12
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#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
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#define TCE_ENTRY_SIZE 8 /* each TCE is 64 bits */
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#define TCE_RPN_MASK 0xfffffffffful /* 40-bit RPN (4K pages) */
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#define TCE_RPN_SHIFT 12
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#define TCE_VALID 0x800 /* TCE valid */
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#define TCE_ALLIO 0x400 /* TCE valid for all lpars */
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#define TCE_PCI_WRITE 0x2 /* write from PCI allowed */
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#define TCE_PCI_READ 0x1 /* read from PCI allowed */
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#define TCE_VB_WRITE 0x1 /* write from VB allowed */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_TCE_H */
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