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48c1cd40fa
As HW SGL can be seen as a data format of QM's sqe, we merge sgl code into qm module and rename it as hisi_qm, which reduces the number of module and make the name less generic. This patch also modify the interface of SGL: - Create/free hisi_acc_sgl_pool inside. - Let user to pass the SGE number in one SGL when creating sgl pool, which is better than a unified module parameter for sgl module before. - Modify zip driver according to sgl interface change. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
34 lines
929 B
Plaintext
34 lines
929 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CRYPTO_DEV_HISI_SEC
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tristate "Support for Hisilicon SEC crypto block cipher accelerator"
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select CRYPTO_BLKCIPHER
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select CRYPTO_ALGAPI
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select CRYPTO_LIB_DES
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select SG_SPLIT
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depends on ARM64 || COMPILE_TEST
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depends on HAS_IOMEM
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help
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Support for Hisilicon SEC Engine in Hip06 and Hip07
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To compile this as a module, choose M here: the module
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will be called hisi_sec.
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config CRYPTO_DEV_HISI_QM
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tristate
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depends on ARM64 || COMPILE_TEST
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depends on PCI && PCI_MSI
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help
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HiSilicon accelerator engines use a common queue management
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interface. Specific engine driver may use this module.
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config CRYPTO_DEV_HISI_ZIP
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tristate "Support for HiSilicon ZIP accelerator"
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depends on PCI && PCI_MSI
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depends on ARM64 || (COMPILE_TEST && 64BIT)
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depends on !CPU_BIG_ENDIAN || COMPILE_TEST
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select CRYPTO_DEV_HISI_QM
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select SG_SPLIT
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help
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Support for HiSilicon ZIP Driver
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