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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c8a8309049
The Allwinner H6 SoC has two pin controllers, one main controller (called CPUX-PORT in user manual) and one controller in CPUs power domain (called CPUS-PORT in user manual). This commit introduces support for the main pin controller on H6. The pin bank A and B are not wired out and hidden from the SoC's documents, however it's shown that the "ATE" (an AC200 chip co-packaged with the H6 die) is connected to the main SoC die via these pin banks. The information about these banks is just copied from the BSP pinctrl driver, but re-formatted to fit the mainline pinctrl driver format. The GPIO functions are dropped, as they're impossible to use -- except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
85 lines
1.5 KiB
Plaintext
85 lines
1.5 KiB
Plaintext
if ARCH_SUNXI
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config PINCTRL_SUNXI
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bool
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select PINMUX
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select GENERIC_PINCONF
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select GPIOLIB
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config PINCTRL_SUN4I_A10
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def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN5I
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def_bool MACH_SUN5I
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select PINCTRL_SUNXI
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config PINCTRL_SUN6I_A31
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def_bool MACH_SUN6I
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select PINCTRL_SUNXI
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config PINCTRL_SUN6I_A31_R
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def_bool MACH_SUN6I
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depends on RESET_CONTROLLER
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_A23
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_A33
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_A83T
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_A83T_R
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_A23_R
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def_bool MACH_SUN8I
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depends on RESET_CONTROLLER
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_H3
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_H3_R
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def_bool MACH_SUN8I || (ARM64 && ARCH_SUNXI)
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_V3S
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN9I_A80
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def_bool MACH_SUN9I
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select PINCTRL_SUNXI
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config PINCTRL_SUN9I_A80_R
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def_bool MACH_SUN9I
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depends on RESET_CONTROLLER
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select PINCTRL_SUNXI
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config PINCTRL_SUN50I_A64
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def_bool ARM64 && ARCH_SUNXI
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select PINCTRL_SUNXI
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config PINCTRL_SUN50I_A64_R
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def_bool ARM64 && ARCH_SUNXI
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select PINCTRL_SUNXI
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config PINCTRL_SUN50I_H5
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def_bool ARM64 && ARCH_SUNXI
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select PINCTRL_SUNXI
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config PINCTRL_SUN50I_H6
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def_bool ARM64 && ARCH_SUNXI
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select PINCTRL_SUNXI
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endif
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