Stafford Horne 489e0f802d openrisc: add 1 and 2 byte cmpxchg support ... OpenRISC only supports hardware instructions that perform 4 byte atomic operations. For enabling qrwlocks for upcoming SMP support 1 and 2 byte implementations are needed. To do this we leverage the 4 byte atomic operations and shift/mask the 1 and 2 byte areas as needed. This heavily borrows ideas and routines from sh and mips, which do something similar. Cc: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Stafford Horne <shorne@gmail.com>		2017-11-03 14:01:12 +09:00
..
asm	openrisc: add 1 and 2 byte cmpxchg support	2017-11-03 14:01:12 +09:00
uapi/asm	openrisc: move generic-y of exported headers to uapi/asm/Kbuild	2017-07-11 21:33:50 +09:00