mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 05:56:39 +07:00
8ccb49dd5c
Add tracepoints for cppi41 dma channels. Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
713 lines
19 KiB
C
713 lines
19 KiB
C
#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/sizes.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include "cppi_dma.h"
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#include "musb_core.h"
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#include "musb_trace.h"
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#define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
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#define EP_MODE_AUTOREQ_NONE 0
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#define EP_MODE_AUTOREQ_ALL_NEOP 1
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#define EP_MODE_AUTOREQ_ALWAYS 3
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#define EP_MODE_DMA_TRANSPARENT 0
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#define EP_MODE_DMA_RNDIS 1
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#define EP_MODE_DMA_GEN_RNDIS 3
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#define USB_CTRL_TX_MODE 0x70
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#define USB_CTRL_RX_MODE 0x74
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#define USB_CTRL_AUTOREQ 0xd0
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#define USB_TDOWN 0xd8
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#define MUSB_DMA_NUM_CHANNELS 15
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struct cppi41_dma_controller {
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struct dma_controller controller;
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struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
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struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
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struct musb *musb;
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struct hrtimer early_tx;
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struct list_head early_tx_list;
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u32 rx_mode;
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u32 tx_mode;
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u32 auto_req;
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};
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static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
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{
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u16 csr;
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u8 toggle;
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if (cppi41_channel->is_tx)
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return;
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if (!is_host_active(cppi41_channel->controller->musb))
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return;
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csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
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toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
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cppi41_channel->usb_toggle = toggle;
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}
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static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
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{
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struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
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struct musb *musb = hw_ep->musb;
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u16 csr;
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u8 toggle;
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if (cppi41_channel->is_tx)
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return;
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if (!is_host_active(musb))
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return;
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musb_ep_select(musb->mregs, hw_ep->epnum);
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csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
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toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
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/*
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* AM335x Advisory 1.0.13: Due to internal synchronisation error the
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* data toggle may reset from DATA1 to DATA0 during receiving data from
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* more than one endpoint.
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*/
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if (!toggle && toggle == cppi41_channel->usb_toggle) {
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csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
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musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
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musb_dbg(cppi41_channel->controller->musb,
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"Restoring DATA1 toggle.");
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}
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cppi41_channel->usb_toggle = toggle;
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}
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static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
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{
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u8 epnum = hw_ep->epnum;
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struct musb *musb = hw_ep->musb;
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void __iomem *epio = musb->endpoints[epnum].regs;
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u16 csr;
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musb_ep_select(musb->mregs, hw_ep->epnum);
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csr = musb_readw(epio, MUSB_TXCSR);
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if (csr & MUSB_TXCSR_TXPKTRDY)
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return false;
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return true;
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}
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static void cppi41_dma_callback(void *private_data);
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static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
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{
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struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
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struct musb *musb = hw_ep->musb;
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void __iomem *epio = hw_ep->regs;
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u16 csr;
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if (!cppi41_channel->prog_len ||
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(cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)) {
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/* done, complete */
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cppi41_channel->channel.actual_len =
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cppi41_channel->transferred;
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cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
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cppi41_channel->channel.rx_packet_done = true;
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/*
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* transmit ZLP using PIO mode for transfers which size is
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* multiple of EP packet size.
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*/
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if (cppi41_channel->tx_zlp && (cppi41_channel->transferred %
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cppi41_channel->packet_sz) == 0) {
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musb_ep_select(musb->mregs, hw_ep->epnum);
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csr = MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY;
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musb_writew(epio, MUSB_TXCSR, csr);
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}
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trace_musb_cppi41_done(cppi41_channel);
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musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
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} else {
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/* next iteration, reload */
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struct dma_chan *dc = cppi41_channel->dc;
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struct dma_async_tx_descriptor *dma_desc;
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enum dma_transfer_direction direction;
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u32 remain_bytes;
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cppi41_channel->buf_addr += cppi41_channel->packet_sz;
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remain_bytes = cppi41_channel->total_len;
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remain_bytes -= cppi41_channel->transferred;
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remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
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cppi41_channel->prog_len = remain_bytes;
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direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
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: DMA_DEV_TO_MEM;
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dma_desc = dmaengine_prep_slave_single(dc,
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cppi41_channel->buf_addr,
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remain_bytes,
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direction,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (WARN_ON(!dma_desc))
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return;
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dma_desc->callback = cppi41_dma_callback;
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dma_desc->callback_param = &cppi41_channel->channel;
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cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
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trace_musb_cppi41_cont(cppi41_channel);
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dma_async_issue_pending(dc);
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if (!cppi41_channel->is_tx) {
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musb_ep_select(musb->mregs, hw_ep->epnum);
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csr = musb_readw(epio, MUSB_RXCSR);
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csr |= MUSB_RXCSR_H_REQPKT;
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musb_writew(epio, MUSB_RXCSR, csr);
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}
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}
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}
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static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
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{
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struct cppi41_dma_controller *controller;
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struct cppi41_dma_channel *cppi41_channel, *n;
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struct musb *musb;
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unsigned long flags;
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enum hrtimer_restart ret = HRTIMER_NORESTART;
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controller = container_of(timer, struct cppi41_dma_controller,
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early_tx);
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musb = controller->musb;
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spin_lock_irqsave(&musb->lock, flags);
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list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
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tx_check) {
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bool empty;
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struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
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empty = musb_is_tx_fifo_empty(hw_ep);
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if (empty) {
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list_del_init(&cppi41_channel->tx_check);
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cppi41_trans_done(cppi41_channel);
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}
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}
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if (!list_empty(&controller->early_tx_list) &&
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!hrtimer_is_queued(&controller->early_tx)) {
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ret = HRTIMER_RESTART;
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hrtimer_forward_now(&controller->early_tx,
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ktime_set(0, 20 * NSEC_PER_USEC));
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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return ret;
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}
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static void cppi41_dma_callback(void *private_data)
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{
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struct dma_channel *channel = private_data;
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struct cppi41_dma_channel *cppi41_channel = channel->private_data;
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struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
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struct cppi41_dma_controller *controller;
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struct musb *musb = hw_ep->musb;
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unsigned long flags;
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struct dma_tx_state txstate;
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u32 transferred;
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int is_hs = 0;
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bool empty;
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spin_lock_irqsave(&musb->lock, flags);
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dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
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&txstate);
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transferred = cppi41_channel->prog_len - txstate.residue;
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cppi41_channel->transferred += transferred;
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trace_musb_cppi41_gb(cppi41_channel);
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update_rx_toggle(cppi41_channel);
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if (cppi41_channel->transferred == cppi41_channel->total_len ||
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transferred < cppi41_channel->packet_sz)
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cppi41_channel->prog_len = 0;
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if (cppi41_channel->is_tx)
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empty = musb_is_tx_fifo_empty(hw_ep);
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if (!cppi41_channel->is_tx || empty) {
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cppi41_trans_done(cppi41_channel);
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goto out;
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}
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/*
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* On AM335x it has been observed that the TX interrupt fires
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* too early that means the TXFIFO is not yet empty but the DMA
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* engine says that it is done with the transfer. We don't
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* receive a FIFO empty interrupt so the only thing we can do is
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* to poll for the bit. On HS it usually takes 2us, on FS around
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* 110us - 150us depending on the transfer size.
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* We spin on HS (no longer than than 25us and setup a timer on
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* FS to check for the bit and complete the transfer.
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*/
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controller = cppi41_channel->controller;
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if (is_host_active(musb)) {
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if (musb->port1_status & USB_PORT_STAT_HIGH_SPEED)
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is_hs = 1;
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} else {
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if (musb->g.speed == USB_SPEED_HIGH)
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is_hs = 1;
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}
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if (is_hs) {
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unsigned wait = 25;
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do {
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empty = musb_is_tx_fifo_empty(hw_ep);
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if (empty) {
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cppi41_trans_done(cppi41_channel);
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goto out;
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}
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wait--;
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if (!wait)
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break;
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cpu_relax();
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} while (1);
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}
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list_add_tail(&cppi41_channel->tx_check,
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&controller->early_tx_list);
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if (!hrtimer_is_queued(&controller->early_tx)) {
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unsigned long usecs = cppi41_channel->total_len / 10;
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hrtimer_start_range_ns(&controller->early_tx,
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ktime_set(0, usecs * NSEC_PER_USEC),
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20 * NSEC_PER_USEC,
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HRTIMER_MODE_REL);
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}
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out:
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
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{
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unsigned shift;
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shift = (ep - 1) * 2;
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old &= ~(3 << shift);
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old |= mode << shift;
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return old;
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}
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static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
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unsigned mode)
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{
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struct cppi41_dma_controller *controller = cppi41_channel->controller;
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u32 port;
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u32 new_mode;
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u32 old_mode;
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if (cppi41_channel->is_tx)
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old_mode = controller->tx_mode;
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else
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old_mode = controller->rx_mode;
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port = cppi41_channel->port_num;
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new_mode = update_ep_mode(port, mode, old_mode);
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if (new_mode == old_mode)
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return;
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if (cppi41_channel->is_tx) {
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controller->tx_mode = new_mode;
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musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
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new_mode);
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} else {
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controller->rx_mode = new_mode;
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musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
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new_mode);
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}
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}
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static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
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unsigned mode)
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{
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struct cppi41_dma_controller *controller = cppi41_channel->controller;
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u32 port;
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u32 new_mode;
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u32 old_mode;
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old_mode = controller->auto_req;
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port = cppi41_channel->port_num;
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new_mode = update_ep_mode(port, mode, old_mode);
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if (new_mode == old_mode)
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return;
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controller->auto_req = new_mode;
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musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
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}
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static bool cppi41_configure_channel(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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struct cppi41_dma_channel *cppi41_channel = channel->private_data;
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struct dma_chan *dc = cppi41_channel->dc;
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struct dma_async_tx_descriptor *dma_desc;
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enum dma_transfer_direction direction;
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struct musb *musb = cppi41_channel->controller->musb;
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unsigned use_gen_rndis = 0;
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cppi41_channel->buf_addr = dma_addr;
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cppi41_channel->total_len = len;
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cppi41_channel->transferred = 0;
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cppi41_channel->packet_sz = packet_sz;
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cppi41_channel->tx_zlp = (cppi41_channel->is_tx && mode) ? 1 : 0;
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/*
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* Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
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* than max packet size at a time.
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*/
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if (cppi41_channel->is_tx)
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use_gen_rndis = 1;
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if (use_gen_rndis) {
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/* RNDIS mode */
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if (len > packet_sz) {
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musb_writel(musb->ctrl_base,
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RNDIS_REG(cppi41_channel->port_num), len);
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/* gen rndis */
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cppi41_set_dma_mode(cppi41_channel,
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EP_MODE_DMA_GEN_RNDIS);
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/* auto req */
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cppi41_set_autoreq_mode(cppi41_channel,
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EP_MODE_AUTOREQ_ALL_NEOP);
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} else {
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musb_writel(musb->ctrl_base,
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RNDIS_REG(cppi41_channel->port_num), 0);
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cppi41_set_dma_mode(cppi41_channel,
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EP_MODE_DMA_TRANSPARENT);
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cppi41_set_autoreq_mode(cppi41_channel,
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EP_MODE_AUTOREQ_NONE);
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}
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} else {
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/* fallback mode */
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cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
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cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREQ_NONE);
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len = min_t(u32, packet_sz, len);
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}
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cppi41_channel->prog_len = len;
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direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
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dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!dma_desc)
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return false;
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dma_desc->callback = cppi41_dma_callback;
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dma_desc->callback_param = channel;
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cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
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cppi41_channel->channel.rx_packet_done = false;
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trace_musb_cppi41_config(cppi41_channel);
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save_rx_toggle(cppi41_channel);
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dma_async_issue_pending(dc);
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return true;
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}
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static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
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struct musb_hw_ep *hw_ep, u8 is_tx)
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{
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struct cppi41_dma_controller *controller = container_of(c,
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struct cppi41_dma_controller, controller);
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struct cppi41_dma_channel *cppi41_channel = NULL;
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u8 ch_num = hw_ep->epnum - 1;
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if (ch_num >= MUSB_DMA_NUM_CHANNELS)
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return NULL;
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if (is_tx)
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cppi41_channel = &controller->tx_channel[ch_num];
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else
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cppi41_channel = &controller->rx_channel[ch_num];
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if (!cppi41_channel->dc)
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return NULL;
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if (cppi41_channel->is_allocated)
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return NULL;
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cppi41_channel->hw_ep = hw_ep;
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cppi41_channel->is_allocated = 1;
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trace_musb_cppi41_alloc(cppi41_channel);
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return &cppi41_channel->channel;
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}
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static void cppi41_dma_channel_release(struct dma_channel *channel)
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{
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struct cppi41_dma_channel *cppi41_channel = channel->private_data;
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trace_musb_cppi41_free(cppi41_channel);
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if (cppi41_channel->is_allocated) {
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cppi41_channel->is_allocated = 0;
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channel->status = MUSB_DMA_STATUS_FREE;
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channel->actual_len = 0;
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}
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}
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static int cppi41_dma_channel_program(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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int ret;
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struct cppi41_dma_channel *cppi41_channel = channel->private_data;
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int hb_mult = 0;
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BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
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|
channel->status == MUSB_DMA_STATUS_BUSY);
|
|
|
|
if (is_host_active(cppi41_channel->controller->musb)) {
|
|
if (cppi41_channel->is_tx)
|
|
hb_mult = cppi41_channel->hw_ep->out_qh->hb_mult;
|
|
else
|
|
hb_mult = cppi41_channel->hw_ep->in_qh->hb_mult;
|
|
}
|
|
|
|
channel->status = MUSB_DMA_STATUS_BUSY;
|
|
channel->actual_len = 0;
|
|
|
|
if (hb_mult)
|
|
packet_sz = hb_mult * (packet_sz & 0x7FF);
|
|
|
|
ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
|
|
if (!ret)
|
|
channel->status = MUSB_DMA_STATUS_FREE;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
|
|
void *buf, u32 length)
|
|
{
|
|
struct cppi41_dma_channel *cppi41_channel = channel->private_data;
|
|
struct cppi41_dma_controller *controller = cppi41_channel->controller;
|
|
struct musb *musb = controller->musb;
|
|
|
|
if (is_host_active(musb)) {
|
|
WARN_ON(1);
|
|
return 1;
|
|
}
|
|
if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
|
|
return 0;
|
|
if (cppi41_channel->is_tx)
|
|
return 1;
|
|
/* AM335x Advisory 1.0.13. No workaround for device RX mode */
|
|
return 0;
|
|
}
|
|
|
|
static int cppi41_dma_channel_abort(struct dma_channel *channel)
|
|
{
|
|
struct cppi41_dma_channel *cppi41_channel = channel->private_data;
|
|
struct cppi41_dma_controller *controller = cppi41_channel->controller;
|
|
struct musb *musb = controller->musb;
|
|
void __iomem *epio = cppi41_channel->hw_ep->regs;
|
|
int tdbit;
|
|
int ret;
|
|
unsigned is_tx;
|
|
u16 csr;
|
|
|
|
is_tx = cppi41_channel->is_tx;
|
|
trace_musb_cppi41_abort(cppi41_channel);
|
|
|
|
if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
|
|
return 0;
|
|
|
|
list_del_init(&cppi41_channel->tx_check);
|
|
if (is_tx) {
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
|
csr &= ~MUSB_TXCSR_DMAENAB;
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
} else {
|
|
cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREQ_NONE);
|
|
|
|
/* delay to drain to cppi dma pipeline for isoch */
|
|
udelay(250);
|
|
|
|
csr = musb_readw(epio, MUSB_RXCSR);
|
|
csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
/* wait to drain cppi dma pipe line */
|
|
udelay(50);
|
|
|
|
csr = musb_readw(epio, MUSB_RXCSR);
|
|
if (csr & MUSB_RXCSR_RXPKTRDY) {
|
|
csr |= MUSB_RXCSR_FLUSHFIFO;
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
}
|
|
}
|
|
|
|
tdbit = 1 << cppi41_channel->port_num;
|
|
if (is_tx)
|
|
tdbit <<= 16;
|
|
|
|
do {
|
|
if (is_tx)
|
|
musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
|
|
ret = dmaengine_terminate_all(cppi41_channel->dc);
|
|
} while (ret == -EAGAIN);
|
|
|
|
if (is_tx) {
|
|
musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
|
|
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
|
if (csr & MUSB_TXCSR_TXPKTRDY) {
|
|
csr |= MUSB_TXCSR_FLUSHFIFO;
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
}
|
|
}
|
|
|
|
cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
|
|
return 0;
|
|
}
|
|
|
|
static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
|
|
{
|
|
struct dma_chan *dc;
|
|
int i;
|
|
|
|
for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
|
|
dc = ctrl->tx_channel[i].dc;
|
|
if (dc)
|
|
dma_release_channel(dc);
|
|
dc = ctrl->rx_channel[i].dc;
|
|
if (dc)
|
|
dma_release_channel(dc);
|
|
}
|
|
}
|
|
|
|
static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
|
|
{
|
|
cppi41_release_all_dma_chans(controller);
|
|
}
|
|
|
|
static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
|
|
{
|
|
struct musb *musb = controller->musb;
|
|
struct device *dev = musb->controller;
|
|
struct device_node *np = dev->parent->of_node;
|
|
struct cppi41_dma_channel *cppi41_channel;
|
|
int count;
|
|
int i;
|
|
int ret;
|
|
|
|
count = of_property_count_strings(np, "dma-names");
|
|
if (count < 0)
|
|
return count;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
struct dma_chan *dc;
|
|
struct dma_channel *musb_dma;
|
|
const char *str;
|
|
unsigned is_tx;
|
|
unsigned int port;
|
|
|
|
ret = of_property_read_string_index(np, "dma-names", i, &str);
|
|
if (ret)
|
|
goto err;
|
|
if (strstarts(str, "tx"))
|
|
is_tx = 1;
|
|
else if (strstarts(str, "rx"))
|
|
is_tx = 0;
|
|
else {
|
|
dev_err(dev, "Wrong dmatype %s\n", str);
|
|
goto err;
|
|
}
|
|
ret = kstrtouint(str + 2, 0, &port);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = -EINVAL;
|
|
if (port > MUSB_DMA_NUM_CHANNELS || !port)
|
|
goto err;
|
|
if (is_tx)
|
|
cppi41_channel = &controller->tx_channel[port - 1];
|
|
else
|
|
cppi41_channel = &controller->rx_channel[port - 1];
|
|
|
|
cppi41_channel->controller = controller;
|
|
cppi41_channel->port_num = port;
|
|
cppi41_channel->is_tx = is_tx;
|
|
INIT_LIST_HEAD(&cppi41_channel->tx_check);
|
|
|
|
musb_dma = &cppi41_channel->channel;
|
|
musb_dma->private_data = cppi41_channel;
|
|
musb_dma->status = MUSB_DMA_STATUS_FREE;
|
|
musb_dma->max_len = SZ_4M;
|
|
|
|
dc = dma_request_slave_channel(dev->parent, str);
|
|
if (!dc) {
|
|
dev_err(dev, "Failed to request %s.\n", str);
|
|
ret = -EPROBE_DEFER;
|
|
goto err;
|
|
}
|
|
cppi41_channel->dc = dc;
|
|
}
|
|
return 0;
|
|
err:
|
|
cppi41_release_all_dma_chans(controller);
|
|
return ret;
|
|
}
|
|
|
|
void cppi41_dma_controller_destroy(struct dma_controller *c)
|
|
{
|
|
struct cppi41_dma_controller *controller = container_of(c,
|
|
struct cppi41_dma_controller, controller);
|
|
|
|
hrtimer_cancel(&controller->early_tx);
|
|
cppi41_dma_controller_stop(controller);
|
|
kfree(controller);
|
|
}
|
|
EXPORT_SYMBOL_GPL(cppi41_dma_controller_destroy);
|
|
|
|
struct dma_controller *
|
|
cppi41_dma_controller_create(struct musb *musb, void __iomem *base)
|
|
{
|
|
struct cppi41_dma_controller *controller;
|
|
int ret = 0;
|
|
|
|
if (!musb->controller->parent->of_node) {
|
|
dev_err(musb->controller, "Need DT for the DMA engine.\n");
|
|
return NULL;
|
|
}
|
|
|
|
controller = kzalloc(sizeof(*controller), GFP_KERNEL);
|
|
if (!controller)
|
|
goto kzalloc_fail;
|
|
|
|
hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
|
|
controller->early_tx.function = cppi41_recheck_tx_req;
|
|
INIT_LIST_HEAD(&controller->early_tx_list);
|
|
controller->musb = musb;
|
|
|
|
controller->controller.channel_alloc = cppi41_dma_channel_allocate;
|
|
controller->controller.channel_release = cppi41_dma_channel_release;
|
|
controller->controller.channel_program = cppi41_dma_channel_program;
|
|
controller->controller.channel_abort = cppi41_dma_channel_abort;
|
|
controller->controller.is_compatible = cppi41_is_compatible;
|
|
|
|
ret = cppi41_dma_controller_start(controller);
|
|
if (ret)
|
|
goto plat_get_fail;
|
|
return &controller->controller;
|
|
|
|
plat_get_fail:
|
|
kfree(controller);
|
|
kzalloc_fail:
|
|
if (ret == -EPROBE_DEFER)
|
|
return ERR_PTR(ret);
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(cppi41_dma_controller_create);
|